fpga: lib: Add AXI4 (full) interface
Add a SystemVerilog interface for connecting AXI4 ports, and an associated header file with helper macros. Original-commit: 04d29e85b0c0698e3de96b54fd3f6e04eb439f74
This commit is contained in:
Andrew Moch
committed by
Aaron Rossetto
Aaron Rossetto
parent
d7acf31a38
commit
8cb9bdd331
@@ -0,0 +1,329 @@
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//
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// Copyright 2021 Ettus Research, A National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Interface: AxiIf
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// Description:
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// AXI4 is an ARM standard for bursting memory mapped transfers
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// For more information on the spec see
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// - https://developer.arm.com/docs/ihi0022/d
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//
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// The interface contains methods for
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// (1) Writing an address
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// (2) Reading an address
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//
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// Parameters:
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// - DATA_WIDTH - Width of the data on AXI4 bus
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// - ADDR_WIDTH - Width of the address on AXI4 bus
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//
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//-----------------------------------------------------------------------------
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// AXI4 interface
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//-----------------------------------------------------------------------------
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interface AxiIf #(
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int DATA_WIDTH = 64,
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int ADDR_WIDTH = 1
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) (
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input logic clk,
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input logic rst = 1'b0
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);
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import PkgAxi::*;
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localparam BYTES_PER_WORD = DATA_WIDTH/8;
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// local type defs
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typedef logic [DATA_WIDTH-1:0] data_t;
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typedef logic [ADDR_WIDTH-1:0] addr_t;
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typedef logic [BYTES_PER_WORD-1:0] strb_t;
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typedef logic [7:0] len_t;
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typedef logic [2:0] size_t;
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typedef logic [1:0] burst_t;
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typedef logic [0:0] lock_t;
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typedef logic [3:0] cache_t;
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typedef logic [2:0] prot_t;
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typedef logic [3:0] qos_t;
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// Signals that make up an Axi interface
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// Write Address Channel
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addr_t awaddr;
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len_t awlen;
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size_t awsize;
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burst_t awburst;
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lock_t awlock;
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cache_t awcache;
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prot_t awprot;
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qos_t awqos;
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logic awvalid;
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logic awready;
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// Write Data Channel
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data_t wdata;
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strb_t wstrb = '1;
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logic wlast;
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logic wvalid;
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logic wready;
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// Write Response Channel
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axi_resp_t bresp;
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logic bvalid;
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logic bready;
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// Read Address Channel
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addr_t araddr;
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len_t arlen;
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size_t arsize;
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burst_t arburst;
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lock_t arlock;
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cache_t arcache;
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prot_t arprot;
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qos_t arqos;
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logic arvalid;
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logic arready;
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// Read Data Channel
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data_t rdata;
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axi_resp_t rresp;
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logic rlast;
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logic rvalid;
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logic rready;
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// Master Functions
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task automatic drive_aw(input addr_t addr,
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input len_t len,
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input size_t size,
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input burst_t burst,
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input lock_t lock,
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input cache_t cache,
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input prot_t prot,
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input qos_t qos);
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awaddr = addr;
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awlen = len;
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awsize = size;
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awburst = burst;
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awlock = lock;
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awcache = cache;
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awprot = prot;
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awqos = qos;
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awvalid = 1;
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endtask
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task automatic drive_w(input data_t data,
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input logic last,
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input strb_t strb = '1);
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wdata = data;
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wstrb = strb;
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wlast = last;
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wvalid = 1;
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endtask
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task automatic drive_aw_idle();
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awaddr = 'X;
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awlen = 'X;
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awsize = 'X;
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awburst = 'X;
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awlock = 'X;
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awcache = 'X;
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awprot = 'X;
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awqos = 'X;
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awvalid = 0;
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endtask
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task automatic drive_w_idle();
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wdata = 'X;
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wstrb = 'X;
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wlast = 1'bX;
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wvalid = 0;
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endtask
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task automatic drive_read(input addr_t addr,
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input len_t len,
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input size_t size,
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input burst_t burst,
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input lock_t lock,
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input cache_t cache,
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input prot_t prot,
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input qos_t qos);
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araddr = addr;
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arlen = len;
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arsize = size;
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arburst = burst;
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arlock = lock;
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arcache = cache;
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arprot = prot;
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arqos = qos;
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arvalid = 1;
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endtask
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task automatic drive_read_idle();
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araddr = 'X;
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araddr = 'X;
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arlen = 'X;
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arsize = 'X;
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arburst = 'X;
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arlock = 'X;
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arcache = 'X;
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arprot = 'X;
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arqos = 'X;
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arvalid = 0;
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endtask
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// Slave Functions
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task automatic drive_write_resp(input axi_resp_t resp=OKAY);
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bresp = resp;
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bvalid = 1;
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endtask
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task automatic drive_write_resp_idle();
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bresp = OKAY;
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bvalid = 0;
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endtask
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task automatic drive_read_resp(input data_t data,
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input logic last,
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input axi_resp_t resp=OKAY);
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rdata = data;
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rresp = resp;
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rlast = last;
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rvalid = 1;
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endtask
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task automatic drive_read_resp_idle();
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rdata = 'X;
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rresp = OKAY;
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rlast = 1'bX;
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rvalid = 0;
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endtask
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// View from the master side
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modport master (
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input clk, rst,
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output awaddr,awlen,awsize,awburst,awlock,awcache,awprot,awqos,awvalid,
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wdata,wstrb,wlast,wvalid,
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bready,
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araddr,arlen,arsize,arburst,arlock,arcache,arprot,arqos,arvalid,
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rready,
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input awready,wready,bresp,bvalid,arready,rdata,rresp,rlast,rvalid,
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import drive_aw,
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import drive_w,
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import drive_w_idle,
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import drive_aw_idle,
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import drive_read,
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import drive_read_idle
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);
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// View from the slave side
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modport slave (
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input clk, rst,
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input awaddr,awlen,awsize,awburst,awlock,awcache,awprot,awqos,awvalid,
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wdata,wstrb,wlast,wvalid,
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bready,
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araddr,arlen,arsize,arburst,arlock,arcache,arprot,arqos,arvalid,
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rready,
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output awready,wready,bresp,bvalid,arready,rdata,rresp,rlast,rvalid,
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import drive_write_resp,
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import drive_write_resp_idle,
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import drive_read_resp,
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import drive_read_resp_idle
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);
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endinterface : AxiIf
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// The _v version of the interface does not assign any signals so it may be used
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// in a continuous context. The most common example is when associating members
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// to a regular verilog output port.
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interface AxiIf_v #(
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int DATA_WIDTH = 64,
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int ADDR_WIDTH = 1
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) (
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input logic clk,
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input logic rst = 1'b0
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);
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import PkgAxi::*;
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localparam BYTES_PER_WORD = DATA_WIDTH/8;
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// local type defs
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typedef logic [DATA_WIDTH-1:0] data_t;
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typedef logic [ADDR_WIDTH-1:0] addr_t;
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typedef logic [BYTES_PER_WORD-1:0] strb_t;
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typedef logic [7:0] len_t;
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typedef logic [2:0] size_t;
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typedef logic [1:0] burst_t;
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typedef logic [0:0] lock_t;
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typedef logic [3:0] cache_t;
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typedef logic [2:0] prot_t;
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typedef logic [3:0] qos_t;
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// Signals that make up an Axi interface
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// Write Address Channel
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addr_t awaddr;
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len_t awlen;
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size_t awsize;
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burst_t awburst;
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lock_t awlock;
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cache_t awcache;
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prot_t awprot;
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qos_t awqos;
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logic awvalid;
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logic awready;
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// Write Data Channel
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data_t wdata;
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strb_t wstrb;
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logic wlast;
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logic wvalid;
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logic wready;
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// Write Response Channel
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axi_resp_t bresp;
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logic bvalid;
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logic bready;
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// Read Address Channel
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addr_t araddr;
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len_t arlen;
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size_t arsize;
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burst_t arburst;
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lock_t arlock;
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cache_t arcache;
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prot_t arprot;
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qos_t arqos;
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logic arvalid;
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logic arready;
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// Read Data Channel
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data_t rdata;
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axi_resp_t rresp;
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logic rlast;
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logic rvalid;
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logic rready;
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// View from the master side
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modport master (
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input clk, rst,
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output awaddr,awlen,awsize,awburst,awlock,awcache,awprot,awqos,awvalid,
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wdata,wstrb,wlast,wvalid,
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bready,
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araddr,arlen,arsize,arburst,arlock,arcache,arprot,arqos,arvalid,
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rready,
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input awready,wready,bresp,bvalid,arready,rdata,rresp,rlast,rvalid
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);
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// View from the slave side
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modport slave (
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input clk, rst,
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input awaddr,awlen,awsize,awburst,awlock,awcache,awprot,awqos,awvalid,
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wdata,wstrb,wlast,wvalid,
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bready,
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araddr,arlen,arsize,arburst,arlock,arcache,arprot,arqos,arvalid,
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rready,
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output awready,wready,bresp,bvalid,arready,rdata,rresp,rlast,rvalid
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);
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endinterface : AxiIf_v
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