fpga: x400: zbx: update projects for new ctrlport modules

Original-commit: 95e227edaaacc3eb68937cebcc2ba385eb0997a2

top/x400/dboards/zbx/cpld/lattice/zbx_top_cpld.ldf

@@ -33,9 +33,6 @@
         <Source name="../../../ctrlport_byte_deserializer.v" type="Verilog" type_short="Verilog">
             <Options/>
         </Source>
-        <Source name="../../../../../../lib/rfnoc/utils/ctrlport_splitter.v" type="Verilog" type_short="Verilog">
-            <Options/>
-        </Source>
         <Source name="../../../../../../lib/wb_spi/rtl/verilog/spi_clgen.v" type="Verilog" type_short="Verilog">
             <Options/>
         </Source>
@@ -51,9 +48,6 @@
         <Source name="../../../../cpld/common/spi_slave_to_ctrlport_master.v" type="Verilog" type_short="Verilog">
             <Options/>
         </Source>
-        <Source name="../../../../../../lib/rfnoc/utils/ctrlport_window.v" type="Verilog" type_short="Verilog">
-            <Options/>
-        </Source>
         <Source name="../register_endpoints/atr_controller.v" type="Verilog" type_short="Verilog">
             <Options/>
         </Source>
@@ -75,11 +69,35 @@
         <Source name="../register_endpoints/switch_control.v" type="Verilog" type_short="Verilog">
             <Options/>
         </Source>
-        <Source name="../../../../../../lib/rfnoc/utils/ctrlport_clk_cross.v" type="Verilog" type_short="Verilog">
+        <Source name="../../../../../../lib/rfnoc/core/ctrlport_pkg.sv" type="Verilog" type_short="Verilog">
-            <Options/>
+            <Options VerilogStandard="System Verilog"/>
         </Source>
-        <Source name="../../../../../../lib/rfnoc/utils/ctrlport_combiner.v" type="Verilog" type_short="Verilog">
+        <Source name="../../../../../../lib/rfnoc/core/ctrlport_if.sv" type="Verilog" type_short="Verilog">
-            <Options/>
+            <Options VerilogStandard="System Verilog"/>
+        </Source>
+        <Source name="../../../../../../lib/rfnoc/utils/ctrlport_clk_cross.sv" type="Verilog" type_short="Verilog">
+            <Options VerilogStandard="System Verilog"/>
+        </Source>
+        <Source name="../../../../../../lib/rfnoc/utils/ctrlport_if_clk_cross.sv" type="Verilog" type_short="Verilog">
+            <Options VerilogStandard="System Verilog"/>
+        </Source>
+        <Source name="../../../../../../lib/rfnoc/utils/ctrlport_combiner.sv" type="Verilog" type_short="Verilog">
+            <Options VerilogStandard="System Verilog"/>
+        </Source>
+        <Source name="../../../../../../lib/rfnoc/utils/ctrlport_if_combiner.sv" type="Verilog" type_short="Verilog">
+            <Options VerilogStandard="System Verilog"/>
+        </Source>
+        <Source name="../../../../../../lib/rfnoc/utils/ctrlport_splitter.sv" type="Verilog" type_short="Verilog">
+            <Options VerilogStandard="System Verilog"/>
+        </Source>
+        <Source name="../../../../../../lib/rfnoc/utils/ctrlport_if_splitter.sv" type="Verilog" type_short="Verilog">
+            <Options VerilogStandard="System Verilog"/>
+        </Source>
+        <Source name="../../../../../../lib/rfnoc/utils/ctrlport_window.sv" type="Verilog" type_short="Verilog">
+            <Options VerilogStandard="System Verilog"/>
+        </Source>
+        <Source name="../../../../../../lib/rfnoc/utils/ctrlport_if_window.sv" type="Verilog" type_short="Verilog">
+            <Options VerilogStandard="System Verilog"/>
         </Source>
         <Source name="ip/pll/pll.ipx" type="IPX_Module" type_short="IPX">
             <Options/>

top/x400/dboards/zbx/cpld/quartus/zbx_top_cpld.qsf

@@ -824,15 +824,19 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CH1_TX_LED
 set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to CH1_TX_LED
 
 # The zbx_top_cpld.v has to stand first as it contains a define statement.
-set_global_assignment -name VERILOG_FILE ../zbx_top_cpld.v
+set_global_assignment -name VERILOG_FILE ../zbx_top_cpld.v -new_extractor
-set_global_assignment -name VERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_decoder.v
+set_global_assignment -name SYSTEMVERILOG_FILE ../../../../../../lib/rfnoc/core/ctrlport_if.sv -new_extractor
+set_global_assignment -name SYSTEMVERILOG_FILE ../../../../../../lib/rfnoc/core/ctrlport_pkg.sv -new_extractor
+set_global_assignment -name SYSTEMVERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_decoder.sv -new_extractor
+set_global_assignment -name SYSTEMVERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_if_decoder.sv -new_extractor
 set_global_assignment -name SDC_FILE ../../../../constraints/timing/shared_constants.sdc
 set_global_assignment -name SDC_FILE ../../../../cpld/x410/db_spi_shared_constants.sdc
 set_global_assignment -name SDC_FILE ../zbx_top_cpld.sdc
 set_global_assignment -name VERILOG_FILE ../../../../../../lib/control/synchronizer_impl.v
 set_global_assignment -name VERILOG_FILE ../../../../../../lib/control/synchronizer.v
 set_global_assignment -name VERILOG_FILE ../../../../../../lib/control/reset_sync.v
-set_global_assignment -name VERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_splitter.v
+set_global_assignment -name SYSTEMVERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_splitter.sv -new_extractor
+set_global_assignment -name SYSTEMVERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_if_splitter.sv -new_extractor
 set_global_assignment -name VERILOG_FILE ../../../../cpld/common/spi_slave.v
 set_global_assignment -name VERILOG_FILE ../../../../cpld/common/spi_slave_to_ctrlport_master.v
 set_global_assignment -name VERILOG_FILE ../register_endpoints/basic_regs.v
@@ -846,15 +850,18 @@ set_global_assignment -name VERILOG_FILE ../../../../../../lib/wb_spi/rtl/verilo
 set_global_assignment -name VERILOG_FILE ../register_endpoints/lo_control.v
 set_global_assignment -name VERILOG_FILE ../zbx_cpld_core.v
 set_global_assignment -name VERILOG_FILE ../../../ctrlport_byte_deserializer.v
-set_global_assignment -name VERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_clk_cross.v
+set_global_assignment -name SYSTEMVERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_clk_cross.sv -new_extractor
+set_global_assignment -name SYSTEMVERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_if_clk_cross.sv -new_extractor
 set_global_assignment -name VERILOG_FILE ../../../../cpld/common/reconfig_engine.v
-set_global_assignment -name VERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_combiner.v
+set_global_assignment -name SYSTEMVERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_combiner.sv -new_extractor
+set_global_assignment -name SYSTEMVERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_if_combiner.sv -new_extractor
 set_global_assignment -name VERILOG_FILE ../register_endpoints/atr_controller.v
 set_global_assignment -name VERILOG_INCLUDE_FILE ../../../../../../lib/control/ram_2port_impl.vh
 set_global_assignment -name VERILOG_FILE ../../../../../../lib/control/ram_2port.v
 set_global_assignment -name VERILOG_FILE ../../../../../../lib/control/handshake.v
 set_global_assignment -name VERILOG_FILE ../../../../../../lib/control/pulse_synchronizer.v
-set_global_assignment -name VERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_window.v
+set_global_assignment -name SYSTEMVERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_window.sv -new_extractor
+set_global_assignment -name SYSTEMVERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_if_window.sv -new_extractor
 
 set_global_assignment -name QSYS_FILE ../ip/on_chip_flash/on_chip_flash.qsys
 set_global_assignment -name QSYS_FILE ../ip/osc/osc.qsys
@@ -884,6 +891,7 @@ set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %"
 
 set_global_assignment -name TOP_LEVEL_ENTITY zbx_top_cpld
 
-
+set_global_assignment -name HYBRID_FLOW_NEW_EXTRACTOR ON
+set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
 
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top