From 88d7598bfc7f4a399fb5330b64e6d2ecd5e28d3e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Max=20K=C3=B6hler?= Date: Fri, 21 Mar 2025 09:06:25 -0500 Subject: [PATCH] fpga: x400: zbx: update projects for new ctrlport modules Original-commit: 95e227edaaacc3eb68937cebcc2ba385eb0997a2 --- .../dboards/zbx/cpld/lattice/zbx_top_cpld.ldf | 38 ++++++++++++++----- .../dboards/zbx/cpld/quartus/zbx_top_cpld.qsf | 22 +++++++---- 2 files changed, 43 insertions(+), 17 deletions(-) diff --git a/top/x400/dboards/zbx/cpld/lattice/zbx_top_cpld.ldf b/top/x400/dboards/zbx/cpld/lattice/zbx_top_cpld.ldf index 6707df4..29027b2 100644 --- a/top/x400/dboards/zbx/cpld/lattice/zbx_top_cpld.ldf +++ b/top/x400/dboards/zbx/cpld/lattice/zbx_top_cpld.ldf @@ -33,9 +33,6 @@ - - - @@ -51,9 +48,6 @@ - - - @@ -75,11 +69,35 @@ - - + + - - + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/top/x400/dboards/zbx/cpld/quartus/zbx_top_cpld.qsf b/top/x400/dboards/zbx/cpld/quartus/zbx_top_cpld.qsf index 126b141..c90a949 100644 --- a/top/x400/dboards/zbx/cpld/quartus/zbx_top_cpld.qsf +++ b/top/x400/dboards/zbx/cpld/quartus/zbx_top_cpld.qsf @@ -824,15 +824,19 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CH1_TX_LED set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to CH1_TX_LED # The zbx_top_cpld.v has to stand first as it contains a define statement. -set_global_assignment -name VERILOG_FILE ../zbx_top_cpld.v -set_global_assignment -name VERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_decoder.v +set_global_assignment -name VERILOG_FILE ../zbx_top_cpld.v -new_extractor +set_global_assignment -name SYSTEMVERILOG_FILE ../../../../../../lib/rfnoc/core/ctrlport_if.sv -new_extractor +set_global_assignment -name SYSTEMVERILOG_FILE ../../../../../../lib/rfnoc/core/ctrlport_pkg.sv -new_extractor +set_global_assignment -name SYSTEMVERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_decoder.sv -new_extractor +set_global_assignment -name SYSTEMVERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_if_decoder.sv -new_extractor set_global_assignment -name SDC_FILE ../../../../constraints/timing/shared_constants.sdc set_global_assignment -name SDC_FILE ../../../../cpld/x410/db_spi_shared_constants.sdc set_global_assignment -name SDC_FILE ../zbx_top_cpld.sdc set_global_assignment -name VERILOG_FILE ../../../../../../lib/control/synchronizer_impl.v set_global_assignment -name VERILOG_FILE ../../../../../../lib/control/synchronizer.v set_global_assignment -name VERILOG_FILE ../../../../../../lib/control/reset_sync.v -set_global_assignment -name VERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_splitter.v +set_global_assignment -name SYSTEMVERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_splitter.sv -new_extractor +set_global_assignment -name SYSTEMVERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_if_splitter.sv -new_extractor set_global_assignment -name VERILOG_FILE ../../../../cpld/common/spi_slave.v set_global_assignment -name VERILOG_FILE ../../../../cpld/common/spi_slave_to_ctrlport_master.v set_global_assignment -name VERILOG_FILE ../register_endpoints/basic_regs.v @@ -846,15 +850,18 @@ set_global_assignment -name VERILOG_FILE ../../../../../../lib/wb_spi/rtl/verilo set_global_assignment -name VERILOG_FILE ../register_endpoints/lo_control.v set_global_assignment -name VERILOG_FILE ../zbx_cpld_core.v set_global_assignment -name VERILOG_FILE ../../../ctrlport_byte_deserializer.v -set_global_assignment -name VERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_clk_cross.v +set_global_assignment -name SYSTEMVERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_clk_cross.sv -new_extractor +set_global_assignment -name SYSTEMVERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_if_clk_cross.sv -new_extractor set_global_assignment -name VERILOG_FILE ../../../../cpld/common/reconfig_engine.v -set_global_assignment -name VERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_combiner.v +set_global_assignment -name SYSTEMVERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_combiner.sv -new_extractor +set_global_assignment -name SYSTEMVERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_if_combiner.sv -new_extractor set_global_assignment -name VERILOG_FILE ../register_endpoints/atr_controller.v set_global_assignment -name VERILOG_INCLUDE_FILE ../../../../../../lib/control/ram_2port_impl.vh set_global_assignment -name VERILOG_FILE ../../../../../../lib/control/ram_2port.v set_global_assignment -name VERILOG_FILE ../../../../../../lib/control/handshake.v set_global_assignment -name VERILOG_FILE ../../../../../../lib/control/pulse_synchronizer.v -set_global_assignment -name VERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_window.v +set_global_assignment -name SYSTEMVERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_window.sv -new_extractor +set_global_assignment -name SYSTEMVERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_if_window.sv -new_extractor set_global_assignment -name QSYS_FILE ../ip/on_chip_flash/on_chip_flash.qsys set_global_assignment -name QSYS_FILE ../ip/osc/osc.qsys @@ -884,6 +891,7 @@ set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %" set_global_assignment -name TOP_LEVEL_ENTITY zbx_top_cpld - +set_global_assignment -name HYBRID_FLOW_NEW_EXTRACTOR ON +set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top