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fpga: x400: zbx: update projects for new ctrlport modules

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Original-commit: 95e227edaaacc3eb68937cebcc2ba385eb0997a2
This commit is contained in:
Max Köhler
2025-03-21 09:09:09 -05:00
committed by Wade Fife
parent 01d6ebd45e
commit 88d7598bfc
2 changed files with 43 additions and 17 deletions
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top/x400/dboards/zbx/cpld/lattice/zbx_top_cpld.ldf
+28 -10
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@@ -33,9 +33,6 @@
<Source name="../../../ctrlport_byte_deserializer.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../../../../../../lib/rfnoc/utils/ctrlport_splitter.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../../../../../../lib/wb_spi/rtl/verilog/spi_clgen.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
@@ -51,9 +48,6 @@
<Source name="../../../../cpld/common/spi_slave_to_ctrlport_master.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../../../../../../lib/rfnoc/utils/ctrlport_window.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../register_endpoints/atr_controller.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
@@ -75,11 +69,35 @@
<Source name="../register_endpoints/switch_control.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../../../../../../lib/rfnoc/utils/ctrlport_clk_cross.v" type="Verilog" type_short="Verilog">
<Options/>
<Source name="../../../../../../lib/rfnoc/core/ctrlport_pkg.sv" type="Verilog" type_short="Verilog">
<Options VerilogStandard="System Verilog"/>
</Source>
<Source name="../../../../../../lib/rfnoc/utils/ctrlport_combiner.v" type="Verilog" type_short="Verilog">
<Options/>
<Source name="../../../../../../lib/rfnoc/core/ctrlport_if.sv" type="Verilog" type_short="Verilog">
<Options VerilogStandard="System Verilog"/>
</Source>
<Source name="../../../../../../lib/rfnoc/utils/ctrlport_clk_cross.sv" type="Verilog" type_short="Verilog">
<Options VerilogStandard="System Verilog"/>
</Source>
<Source name="../../../../../../lib/rfnoc/utils/ctrlport_if_clk_cross.sv" type="Verilog" type_short="Verilog">
<Options VerilogStandard="System Verilog"/>
</Source>
<Source name="../../../../../../lib/rfnoc/utils/ctrlport_combiner.sv" type="Verilog" type_short="Verilog">
<Options VerilogStandard="System Verilog"/>
</Source>
<Source name="../../../../../../lib/rfnoc/utils/ctrlport_if_combiner.sv" type="Verilog" type_short="Verilog">
<Options VerilogStandard="System Verilog"/>
</Source>
<Source name="../../../../../../lib/rfnoc/utils/ctrlport_splitter.sv" type="Verilog" type_short="Verilog">
<Options VerilogStandard="System Verilog"/>
</Source>
<Source name="../../../../../../lib/rfnoc/utils/ctrlport_if_splitter.sv" type="Verilog" type_short="Verilog">
<Options VerilogStandard="System Verilog"/>
</Source>
<Source name="../../../../../../lib/rfnoc/utils/ctrlport_window.sv" type="Verilog" type_short="Verilog">
<Options VerilogStandard="System Verilog"/>
</Source>
<Source name="../../../../../../lib/rfnoc/utils/ctrlport_if_window.sv" type="Verilog" type_short="Verilog">
<Options VerilogStandard="System Verilog"/>
</Source>
<Source name="ip/pll/pll.ipx" type="IPX_Module" type_short="IPX">
<Options/>