fpga: lib: add extended spi core for 64bit

The existing SPI core (simple_spi_slave.v) was limited to 32 bit. This commit adds a second spi core with capability to transfer up to 64 bits while keeping the same amount of resources when using generic setting MAX_BITS = 32. Furthermore, the new module aligns mosi and miso with the edges of sclk. The register stages were not aligned in the existing version. Original-commit: 366cab1fef44f1132a2acf8046ecaeac80793ccc
2020-06-17 07:13:20 -05:00
parent 2a8ec5df90
commit 8875582763
2 changed files with 287 additions and 0 deletions
@@ -39,6 +39,7 @@ settings_bus_mux.v \
 settings_bus_timed_2clk.v \
 simple_i2c_core.v \
 simple_spi_core.v \
+simple_spi_core_64bit.v \
 synchronizer_impl.v \
 synchronizer.v \
 pulse_synchronizer.v \