utils: image builder: Major update
Most important effect of this change: rfnoc_image_builder is now required to build bitfiles, 'make' alone won't suffice any longer! This is a huge changeset to the image builder that combines multiple new features: - There no longer is a separate edge file for the static router. The static routes are generated as a Verilog parameter directly into the rfnoc_core_kernel (which is also modified). - image_builder.py is split up into several smaller files. Code is moved into yaml_utils.py, and the new files grc.py, builder_config.py - Generic module support is added. Aside from noc blocks and stream endpoints, we can now instantiate arbitrary modules (they also require a YAML description file). - To enable such modules, resets are now also tracked the same way that clock domains are. - The ImageBuilderConfig config object now more closes matches the original YAML file. The attributes 'clk_domain_con' and 'block_con' are removed. Instead, the attributes 'connections' and 'clk_domains' are sanitized and amended with extra annotations. The templates are updated to reflect this change. - IO ports can now carry parameters, e.g., to have variable wire widths based on the configuration. - Many Pylint warnings were resolved. - Add inheritance support for image core YAML files. This allows image core files to (recursively) inherit from other image core files. To do so, simply put an 'inherit' entry at the top of the file: ```yaml inherit: 'x410_radio_base.yml' ``` - The inheritance feature is used as part of the image core files. - Image core and DTS files are now generated as a build artefact into the build directory. This requires the usage of rfnoc_image_builder to build images. As a consequence, it is no longer required to check in image core Verilog files. - As another consequence, rfnoc_image_builder is required to build bitfiles! - Image flavours are no longer defined through Makefiles, but purely from the image core YAML files. - Remove all image core YAML files that do not generate a shipping image. Because of the inheritance feature and the requirement to use the image builder, it is trivial to add new YAML files. - Add support for transport adapters through the YAML files. Before, transport adapters were inferred from the make target (e.g., X410_X4_200 would have four 10GbE links based on the 'X4' substring). Now, transport adapters are defined via the image core YAML. - This feature is currently only used (or can be used) by the X4xx series. Older devices may or may not be ported to allow custom transport adapters in the future. - Add parameters to the BSP YAMLs and the devices itself. This allows setting global parameters in the image core files. For example, the X4x0 devices use this to decide if they instantiate DRAM channels. - DTS includes and constraint files can now be requested by blocks/transport adapter through their YAML files. They do no longer need to be listed in the Makefile. - Support for secure image cores. These are image cores that allow incorporating RFNoC blocks that require license keys and thus can't live in an open-source environment. This solution adds the option for secure image cores without touching the open source feature set. - Add --reuse option to allow manual editing of generated artefacts - Allow IO signatures from any module: until now IO signatures had to be defined in a single file (io_signatures). This file will persist. In addition each module can add its own IO signature as with the same format the core IO signatures placed under the top level key `io_signatures`. IO signatures are still maintained in a global dictionary. The consequence is that they can be shared among independent modules as well as they have to have a globally unique name. The image builder will warn about detected name clashes for the signatures. - As a consequence, some less commonly used IO signatures were moved to their corresponding module YAML files. Co-authored-by: Wade Fife <wade.fife@ni.com> Co-authored-by: Lars Amsel <lars.amsel@ni.com> Original-commit: a98ce2621e2a2dc25535fc700b49bfcb00b8eb59
This commit is contained in:
Martin Braun
committed by
Joerg Hofrichter
Joerg Hofrichter
co-authored by
Wade Fife
Lars Amsel
Wade Fife
Lars Amsel
parent
77d07a9714
commit
8669c68048
+31
-197
@@ -22,84 +22,24 @@ BUILD_BASE_DIR ?= .
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# Base directory for the build outputs.
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BUILD_OUTPUT_DIR ?= $(BUILD_BASE_DIR)/build
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# Definitions
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# MGT Types from x4xx_mgt_type.vh
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MGT_100GbE = 5
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MGT_Aurora = 3
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MGT_10GbE = 2
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MGT_Disabled = 0
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# For a 4-lane MGT like 100GBE set QSFPx_0=MGT_100GbE and all others to
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# MGT_Disabled. For a 1-lane MGT like 10GbE do not set anything for unused
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# lanes. This ensures something is defined only for the lanes that are used, so
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# that the TX/RX signals are connected. The presence of a define causes TX/RX
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# to be declared, whereas declaring TX/RX on an unused lane will cause an error
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# in bitgen for unconstrained pins after it is optimized out.
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QSFP0_10GBE = QSFP0_0=$(MGT_10GbE)
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QSFP0_4X10GBE = QSFP0_0=$(MGT_10GbE) QSFP0_1=$(MGT_10GbE) QSFP0_2=$(MGT_10GbE) QSFP0_3=$(MGT_10GbE)
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QSFP0_100GBE = QSFP0_0=$(MGT_100GbE) QSFP0_1=$(MGT_Disabled) QSFP0_2=$(MGT_Disabled) QSFP0_3=$(MGT_Disabled)
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QSFP1_10GBE = QSFP1_0=$(MGT_10GbE)
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QSFP1_4X10GBE = QSFP1_0=$(MGT_10GbE) QSFP1_1=$(MGT_10GbE) QSFP1_2=$(MGT_10GbE) QSFP1_3=$(MGT_10GbE)
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QSFP1_100GBE = QSFP1_0=$(MGT_100GbE) QSFP1_1=$(MGT_Disabled) QSFP1_2=$(MGT_Disabled) QSFP1_3=$(MGT_Disabled)
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# Target specific variables
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X410_IP: DEFS += $(QSFP0_10GBE) RF_BW=100
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X410_X1_100: DEFS += $(QSFP0_10GBE) RF_BW=100 RF_CORE_100M=1 DRAM_BANKS=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_XG_100: DEFS += $(QSFP0_10GBE) $(QSFP1_10GBE) RF_BW=100 RF_CORE_100M=1 DRAM_BANKS=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_X4_100: DEFS += $(QSFP0_4X10GBE) RF_BW=100 RF_CORE_100M=1 DRAM_BANKS=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_X4C_100: DEFS += $(QSFP0_4X10GBE) $(QSFP1_100GBE) RF_BW=100 RF_CORE_100M=1 DRAM_BANKS=0 DRAM_CH=0
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X410_C1_100: DEFS += $(QSFP0_100GBE) RF_BW=100 RF_CORE_100M=1 DRAM_BANKS=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_UC_100: DEFS += $(QSFP1_100GBE) RF_BW=100 RF_CORE_100M=1 DRAM_BANKS=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_C1_200: DEFS += $(QSFP0_100GBE) RF_BW=200 RF_CORE_200M=1 DRAM_BANKS=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_UC_200: DEFS += $(QSFP1_100GBE) RF_BW=200 RF_CORE_200M=1 DRAM_BANKS=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_CG_200: DEFS += $(QSFP0_100GBE) $(QSFP1_100GBE) RF_BW=200 RF_CORE_200M=1 DRAM_BANKS=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_X1_200: DEFS += $(QSFP0_10GBE) RF_BW=200 RF_CORE_200M=1 DRAM_BANKS=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_XG_200: DEFS += $(QSFP0_10GBE) $(QSFP1_10GBE) RF_BW=200 RF_CORE_200M=1 DRAM_BANKS=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_X4_200: DEFS += $(QSFP0_4X10GBE) RF_BW=200 RF_CORE_200M=1 DRAM_BANKS=1 DRAM_CH=4*$(DRAM) DRAM_W=64
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X410_X4C_200: DEFS += $(QSFP0_4X10GBE) $(QSFP1_100GBE) RF_BW=200 RF_CORE_200M=1 DRAM_BANKS=0 DRAM_CH=0
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X410_X1_400: DEFS += $(QSFP0_10GBE) RF_BW=400 RF_CORE_400M=1 DRAM_BANKS=2 DRAM_CH=4*$(DRAM) DRAM_W=128
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X410_XG_400: DEFS += $(QSFP0_10GBE) $(QSFP1_10GBE) RF_BW=400 RF_CORE_400M=1 DRAM_BANKS=2 DRAM_CH=4*$(DRAM) DRAM_W=128
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X410_X4_400: DEFS += $(QSFP0_4X10GBE) RF_BW=400 RF_CORE_400M=1 DRAM_BANKS=2 DRAM_CH=4*$(DRAM) DRAM_W=128
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X410_C1_400: DEFS += $(QSFP0_100GBE) RF_BW=400 RF_CORE_400M=1 DRAM_BANKS=0 DRAM_CH=0
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X410_UC_400: DEFS += $(QSFP1_100GBE) RF_BW=400 RF_CORE_400M=1 DRAM_BANKS=0 DRAM_CH=0
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X410_CG_400: DEFS += $(QSFP0_100GBE) $(QSFP1_100GBE) RF_BW=400 RF_CORE_400M=1 DRAM_BANKS=0 DRAM_CH=0
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X440_X4_200: DEFS += $(QSFP0_4X10GBE) RF_BW=200 RF_CORE_FULL=1 DRAM_BANKS=0 DRAM_CH=0
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X440_X1_400: DEFS += $(QSFP0_10GBE) RF_BW=400 RF_CORE_FULL=1 DRAM_BANKS=2 DRAM_CH=8*$(DRAM) DRAM_W=128
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X440_X4_400: DEFS += $(QSFP0_4X10GBE) RF_BW=400 RF_CORE_FULL=1 DRAM_BANKS=2 DRAM_CH=8*$(DRAM) DRAM_W=128
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X440_C1_400: DEFS += $(QSFP0_100GBE) RF_BW=400 RF_CORE_FULL=1 DRAM_BANKS=0 DRAM_CH=0
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X440_CG_400: DEFS += $(QSFP0_100GBE) $(QSFP1_100GBE) RF_BW=400 RF_CORE_FULL=1 DRAM_BANKS=0 DRAM_CH=0
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X440_X1_1600: DEFS += $(QSFP0_10GBE) RF_BW=1600 RF_CORE_FULL=1 DRAM_BANKS=2 DRAM_CH=2*$(DRAM) DRAM_W=512
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X440_X4_1600: DEFS += $(QSFP0_4X10GBE) RF_BW=1600 RF_CORE_FULL=1 DRAM_BANKS=2 DRAM_CH=2*$(DRAM) DRAM_W=512
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X440_C1_1600: DEFS += $(QSFP0_100GBE) RF_BW=1600 RF_CORE_FULL=1 DRAM_BANKS=0 DRAM_CH=0
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X440_CG_1600: DEFS += $(QSFP0_100GBE) $(QSFP1_100GBE) RF_BW=1600 RF_CORE_FULL=1 DRAM_BANKS=0 DRAM_CH=0
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# Sane defaults for IP builds
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X410_IP: DEFS += QSFP0_0=2 RF_BW=100
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X440_IP: DEFS += QSFP0_0=2 RF_BW=400
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# DRAM IP inclusion. Set to 1 to include DRAM memory controller in design, 0 to
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# exclude it. Note that some targets exclude it regardless of this setting.
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DRAM ?= 1
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IMAGE_CORE_NAME ?= usrp_fpga
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DEFS += $(OPTIONS)
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# Initialize a build seed. This can be changed to randomly affect build results.
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BUILD_SEED ?= 0
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DEFS += BUILD_SEED=$(BUILD_SEED)
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# Default value for incremental Vivado build is disabled.
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# Default value for incremental Vivado build is disabled.
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INCR_BUILD ?= 0
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# Defaults specific to the various targets:
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X410_200_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_200_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_200_static_router.hex)
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X410_X4C_200_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_x4c_200_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_x4c_200_static_router.hex)
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X410_CG_200_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_cg_200_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_cg_200_static_router.hex)
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X410_400_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_400_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_400_static_router.hex)
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X410_400_D_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_400_d_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_400_d_static_router.hex)
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X440_200_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x440_200_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x440_200_static_router.hex)
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X440_400_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x440_400_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x440_400_static_router.hex)
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X440_400_D_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x440_400_d_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x440_400_d_static_router.hex)
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X440_1600_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x440_1600_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x440_1600_static_router.hex)
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X440_1600_D_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x440_1600_d_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x440_1600_d_static_router.hex)
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# Option to stop after RTL elaboration. Use this flag as a synthesis check.
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ifndef TARGET
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ifeq ($(CHECK), 1)
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@@ -114,25 +54,31 @@ ifndef TARGET
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endif
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TOP ?= x4xx
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# vivado_build($1=Device, $2=Definitions, $3=Defaults)
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vivado_build = make -f Makefile.x4xx.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" $3 INCR_BUILD=$(INCR_BUILD)
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vivado_ip = make -f Makefile.x4xx.inc viv_ip NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" $3
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ifdef ARTIFACT_DIR
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BUILD_DIR = $(ARTIFACT_DIR)
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endif
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# vivado_build($1=Device, $2=Option)
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# vivado_build($1=Device (X410 or X440), $2=Definitions)
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vivado_build = make -f Makefile.x4xx.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) EXTRA_DEFS="$2" TOP_MODULE=$(TOP) $2 INCR_BUILD=$(INCR_BUILD)
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vivado_ip = make -f Makefile.x4xx.inc viv_ip NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) EXTRA_DEFS="$2" TOP_MODULE=$(TOP) $2
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# vivado_build($1=Device)
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ifeq ($(TARGET),bin)
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post_build = @\
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mkdir -p $(BUILD_OUTPUT_DIR); \
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echo "Exporting bitstream file..."; \
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cp $(BUILD_BASE_DIR)/build-$(1)_$(2)/x4xx.bit $(BUILD_OUTPUT_DIR)/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bit; \
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cp $(ARTIFACT_DIR)/x4xx.bit $(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).bit; \
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echo "Exporting build report..."; \
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cp $(BUILD_BASE_DIR)/build-$(1)_$(2)/build.rpt $(BUILD_OUTPUT_DIR)/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).rpt; \
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echo "Build DONE ... $(1)_$(2)";
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cp $(ARTIFACT_DIR)/build.rpt $(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).rpt; \
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echo "Build DONE ... $(IMAGE_CORE_NAME)";
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else
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post_build = @echo "Skipping bitfile export."
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endif
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##
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##Available Targets
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##-------------|-----------|----|-----------------|-----------------|------------
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##Target | Bandwidth | Ch | QSFP0 | QSFP1 | DRAM
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##-------------|-----------|----|-----------------|-----------------|------------
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@@ -165,124 +111,13 @@ endif
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##* Note: Not all targets are shipped with UHD
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##* Note: Some YAML configurations might not use all available DRAM channels.
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X410_X1_100: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_X1_100.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS))
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$(call post_build,X410,X1_100)
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X410: X410_IP build/$(IMAGE_CORE_NAME).dts
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$(call vivado_build,X410,$(DEFS) X410=1)
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$(call post_build,X410)
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X440: X440_IP build/$(IMAGE_CORE_NAME).dts
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$(call vivado_build,X440,$(DEFS) X440=1)
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$(call post_build,X440)
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X410_XG_100: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_XG_100.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS))
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$(call post_build,X410,XG_100)
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X410_X4_100: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_X4_100.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS))
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$(call post_build,X410,X4_100)
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X410_X4C_100: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_X4C_100.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_X4C_200_DEFAULTS))
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$(call post_build,X410,X4C_100)
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X410_C1_100: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_C1_100.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_CG_200_DEFAULTS))
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$(call post_build,X410,C1_100)
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X410_UC_100: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_UC_100.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_CG_200_DEFAULTS))
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$(call post_build,X410,UC_100)
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X410_X1_200: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_X1_200.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS))
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$(call post_build,X410,X1_200)
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X410_XG_200: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_XG_200.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS))
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$(call post_build,X410,XG_200)
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X410_X4_200: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_X4_200.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS))
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$(call post_build,X410,X4_200)
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X410_X4C_200: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_X4C_200.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_X4C_200_DEFAULTS))
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$(call post_build,X410,X4C_200)
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X410_C1_200: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_C1_200.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_CG_200_DEFAULTS))
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$(call post_build,X410,C1_200)
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X410_UC_200: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_UC_200.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_CG_200_DEFAULTS))
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$(call post_build,X410,UC_200)
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X410_X1_400: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_X1_400.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_D_DEFAULTS))
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$(call post_build,X410,X1_400)
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X410_XG_400: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_XG_400.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_D_DEFAULTS))
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$(call post_build,X410,XG_400)
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X410_X4_400: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_X4_400.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_D_DEFAULTS))
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$(call post_build,X410,X4_400)
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X410_C1_400: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_C1_400.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_DEFAULTS))
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$(call post_build,X410,C1_400)
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X410_UC_400: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_UC_400.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_DEFAULTS))
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$(call post_build,X410,UC_400)
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X410_CG_400: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_CG_400.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_DEFAULTS))
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$(call post_build,X410,CG_400)
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X440_X4_200: X440_IP $(BUILD_OUTPUT_DIR)/usrp_x440_fpga_X4_200.dts
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$(call vivado_build,X440,$(DEFS) X440=1,$(X440_200_DEFAULTS))
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$(call post_build,X440,X4_200)
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X440_X1_400: X440_IP $(BUILD_OUTPUT_DIR)/usrp_x440_fpga_X1_400.dts
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$(call vivado_build,X440,$(DEFS) X440=1,$(X440_400_D_DEFAULTS))
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$(call post_build,X440,X1_400)
|
||||
|
||||
X440_X4_400: X440_IP $(BUILD_OUTPUT_DIR)/usrp_x440_fpga_X4_400.dts
|
||||
$(call vivado_build,X440,$(DEFS) X440=1,$(X440_400_D_DEFAULTS))
|
||||
$(call post_build,X440,X4_400)
|
||||
|
||||
X440_C1_400: X440_IP $(BUILD_OUTPUT_DIR)/usrp_x440_fpga_C1_400.dts
|
||||
$(call vivado_build,X440,$(DEFS) X440=1,$(X440_400_DEFAULTS))
|
||||
$(call post_build,X440,C1_400)
|
||||
|
||||
X440_CG_400: X440_IP $(BUILD_OUTPUT_DIR)/usrp_x440_fpga_CG_400.dts
|
||||
$(call vivado_build,X440,$(DEFS) X440=1,$(X440_400_DEFAULTS))
|
||||
$(call post_build,X440,CG_400)
|
||||
|
||||
X440_X1_1600: X440_IP $(BUILD_OUTPUT_DIR)/usrp_x440_fpga_X1_1600.dts
|
||||
$(call vivado_build,X440,$(DEFS) X440=1,$(X440_1600_D_DEFAULTS))
|
||||
$(call post_build,X440,X1_1600)
|
||||
|
||||
X440_X4_1600: X440_IP $(BUILD_OUTPUT_DIR)/usrp_x440_fpga_X4_1600.dts
|
||||
$(call vivado_build,X440,$(DEFS) X440=1,$(X440_1600_D_DEFAULTS))
|
||||
$(call post_build,X440,X4_1600)
|
||||
|
||||
X440_C1_1600: X440_IP $(BUILD_OUTPUT_DIR)/usrp_x440_fpga_C1_1600.dts
|
||||
$(call vivado_build,X440,$(DEFS) X440=1,$(X440_1600_DEFAULTS))
|
||||
$(call post_build,X440,C1_1600)
|
||||
|
||||
X440_CG_1600: X440_IP $(BUILD_OUTPUT_DIR)/usrp_x440_fpga_CG_1600.dts
|
||||
$(call vivado_build,X440,$(DEFS) X440=1,$(X440_1600_DEFAULTS))
|
||||
$(call post_build,X440,CG_1600)
|
||||
|
||||
##
|
||||
##Experimental Targets
|
||||
##-------------|-----------|----|-----------------|-----------------|------------
|
||||
##Target | Bandwidth | Ch | QSFP0 | QSFP1 | DRAM
|
||||
##-------------|-----------|----|-----------------|-----------------|------------
|
||||
##X410_CG_200 | 200 | 4 | 100 GbE | 100 GbE | 64b x 4 Ch
|
||||
|
||||
X410_CG_200: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_CG_200.dts
|
||||
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_CG_200_DEFAULTS))
|
||||
$(call post_build,X410,CG_200)
|
||||
|
||||
##
|
||||
##Other Make Targets
|
||||
@@ -290,12 +125,12 @@ X410_CG_200: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_CG_200.dts
|
||||
|
||||
.DEFAULT_GOAL := all
|
||||
|
||||
all: X410_X4_200 X410_CG_400 X410_UC_200 X440_X4_200 X440_X4_400 X440_CG_400 X440_X4_1600 X440_CG_1600 ##(Default targets)
|
||||
all: X410_IP
|
||||
|
||||
X410_IP: ##Build IP only.
|
||||
X410_IP: ##Build X410 IP only.
|
||||
+$(call vivado_ip,X410,$(DEFS) X410=1)
|
||||
|
||||
X440_IP: ##Build IP only.
|
||||
X440_IP: ##Build X440 IP only.
|
||||
+$(call vivado_ip,X440,$(DEFS) X440=1)
|
||||
|
||||
$(BUILD_OUTPUT_DIR)/usrp_x410%.dts: dts/*.dts dts/*.dtsi
|
||||
@@ -305,7 +140,7 @@ $(BUILD_OUTPUT_DIR)/usrp_x410%.dts: dts/*.dts dts/*.dtsi
|
||||
--output dts/x410-version-info.dtsi \
|
||||
--components fpga,cpld_ifc,db_gpio_ifc,rf_core_100m,rf_core_400m
|
||||
${CC} -o $@ -C -E -I dts -nostdinc -undef -x assembler-with-cpp -D__DTS__ \
|
||||
$$(python3 tools/get_dts_input.py --target $@)
|
||||
$(ARTIFACT_DIR)/device_tree.dts
|
||||
|
||||
$(BUILD_OUTPUT_DIR)/usrp_x440%.dts: dts/*.dts dts/*.dtsi
|
||||
-mkdir -p $(BUILD_OUTPUT_DIR)
|
||||
@@ -314,17 +149,17 @@ $(BUILD_OUTPUT_DIR)/usrp_x440%.dts: dts/*.dts dts/*.dtsi
|
||||
--output dts/x440-version-info.dtsi \
|
||||
--components fpga,cpld_ifc,db_gpio_ifc,rf_core_full
|
||||
${CC} -o $@ -C -E -I dts -nostdinc -undef -x assembler-with-cpp -D__DTS__ \
|
||||
$$(python3 tools/get_dts_input.py --target $@)
|
||||
$(ARTIFACT_DIR)/device_tree.dts
|
||||
|
||||
clean: ##Clean up all target build outputs.
|
||||
@echo "Cleaning targets..."
|
||||
@rm -rf $(BUILD_BASE_DIR)/build-X4*
|
||||
@rm -rf $(BUILD_BASE_DIR)/build-X* $(BUILD_BASE_DIR)/build-x*
|
||||
@rm -rf $(BUILD_OUTPUT_DIR)
|
||||
|
||||
cleanall: ##Clean up all target and IP build outputs.
|
||||
@echo "Cleaning targets and IP..."
|
||||
@rm -rf build-ip
|
||||
@rm -rf $(BUILD_BASE_DIR)/build-X4*
|
||||
@rm -rf $(BUILD_BASE_DIR)/build-*
|
||||
@rm -rf $(BUILD_OUTPUT_DIR)
|
||||
|
||||
help: ##Show this help message.
|
||||
@@ -334,7 +169,6 @@ help: ##Show this help message.
|
||||
##Supported Options
|
||||
##-----------------
|
||||
##INCR_BUILD=0 Use incremental Vivado build to speed up consecutive runs
|
||||
##DRAM=0 Exclude DDR4 memory controller IP from the FPGA build.
|
||||
##GUI=1 Launch the build in the Vivado GUI.
|
||||
##PROJECT=1 Save Vivado project file, otherwise it's created in memory.
|
||||
##CHECK=1 Launch the syntax checker instead of building a bitfile.
|
||||
|
||||
Reference in New Issue
Block a user