utils: image builder: Major update
Most important effect of this change: rfnoc_image_builder is now required to build bitfiles, 'make' alone won't suffice any longer! This is a huge changeset to the image builder that combines multiple new features: - There no longer is a separate edge file for the static router. The static routes are generated as a Verilog parameter directly into the rfnoc_core_kernel (which is also modified). - image_builder.py is split up into several smaller files. Code is moved into yaml_utils.py, and the new files grc.py, builder_config.py - Generic module support is added. Aside from noc blocks and stream endpoints, we can now instantiate arbitrary modules (they also require a YAML description file). - To enable such modules, resets are now also tracked the same way that clock domains are. - The ImageBuilderConfig config object now more closes matches the original YAML file. The attributes 'clk_domain_con' and 'block_con' are removed. Instead, the attributes 'connections' and 'clk_domains' are sanitized and amended with extra annotations. The templates are updated to reflect this change. - IO ports can now carry parameters, e.g., to have variable wire widths based on the configuration. - Many Pylint warnings were resolved. - Add inheritance support for image core YAML files. This allows image core files to (recursively) inherit from other image core files. To do so, simply put an 'inherit' entry at the top of the file: ```yaml inherit: 'x410_radio_base.yml' ``` - The inheritance feature is used as part of the image core files. - Image core and DTS files are now generated as a build artefact into the build directory. This requires the usage of rfnoc_image_builder to build images. As a consequence, it is no longer required to check in image core Verilog files. - As another consequence, rfnoc_image_builder is required to build bitfiles! - Image flavours are no longer defined through Makefiles, but purely from the image core YAML files. - Remove all image core YAML files that do not generate a shipping image. Because of the inheritance feature and the requirement to use the image builder, it is trivial to add new YAML files. - Add support for transport adapters through the YAML files. Before, transport adapters were inferred from the make target (e.g., X410_X4_200 would have four 10GbE links based on the 'X4' substring). Now, transport adapters are defined via the image core YAML. - This feature is currently only used (or can be used) by the X4xx series. Older devices may or may not be ported to allow custom transport adapters in the future. - Add parameters to the BSP YAMLs and the devices itself. This allows setting global parameters in the image core files. For example, the X4x0 devices use this to decide if they instantiate DRAM channels. - DTS includes and constraint files can now be requested by blocks/transport adapter through their YAML files. They do no longer need to be listed in the Makefile. - Support for secure image cores. These are image cores that allow incorporating RFNoC blocks that require license keys and thus can't live in an open-source environment. This solution adds the option for secure image cores without touching the open source feature set. - Add --reuse option to allow manual editing of generated artefacts - Allow IO signatures from any module: until now IO signatures had to be defined in a single file (io_signatures). This file will persist. In addition each module can add its own IO signature as with the same format the core IO signatures placed under the top level key `io_signatures`. IO signatures are still maintained in a global dictionary. The consequence is that they can be shared among independent modules as well as they have to have a globally unique name. The image builder will warn about detected name clashes for the signatures. - As a consequence, some less commonly used IO signatures were moved to their corresponding module YAML files. Co-authored-by: Wade Fife <wade.fife@ni.com> Co-authored-by: Lars Amsel <lars.amsel@ni.com> Original-commit: a98ce2621e2a2dc25535fc700b49bfcb00b8eb59
This commit is contained in:
Martin Braun
committed by
Joerg Hofrichter
Joerg Hofrichter
co-authored by
Wade Fife
Lars Amsel
Wade Fife
Lars Amsel
parent
77d07a9714
commit
8669c68048
+10
-13
@@ -28,6 +28,8 @@ BUILD_OUTPUT_DIR ?= $(BUILD_BASE_DIR)/build
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# Initialize a build seed. This can be changed to randomly affect build results.
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BUILD_SEED ?= 0
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# The image core name is something like 'usrp_x310_fpga_XG'
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IMAGE_CORE_NAME ?= usrp_fpga
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GIGE_DEFS=BUILD_1G=1 SFP0_1GBE=1 SFP1_1GBE=1 $(OPTIONS) BUILD_SEED=$(BUILD_SEED)
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HG_DEFS=BUILD_1G=1 BUILD_10G=1 SFP0_1GBE=1 SFP1_10GBE=1 $(OPTIONS) BUILD_SEED=$(BUILD_SEED)
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@@ -49,27 +51,22 @@ ifndef TARGET
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endif
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TOP ?= x300
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DEFAULT_IMAGE_CORE_FILE_X300=x300_rfnoc_image_core.v
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DEFAULT_IMAGE_CORE_FILE_X310=x310_rfnoc_image_core.v
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DEFAULT_EDGE_FILE_X300=$(abspath x300_static_router.hex)
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DEFAULT_EDGE_FILE_X310=$(abspath x310_static_router.hex)
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# vivado_build($1=Device, $2=Definitions)
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vivado_build = make -f Makefile.x300.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" DEFAULT_RFNOC_IMAGE_CORE_FILE=$(DEFAULT_IMAGE_CORE_FILE_$1) DEFAULT_EDGE_FILE=$(DEFAULT_EDGE_FILE_$1)
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vivado_ip = make -f Makefile.x300.inc viv_ip NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" DEFAULT_RFNOC_IMAGE_CORE_FILE=$(DEFAULT_IMAGE_CORE_FILE_$1) DEFAULT_EDGE_FILE=$(DEFAULT_EDGE_FILE_$1)
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vivado_build = make -f Makefile.x300.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2"
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vivado_ip = make -f Makefile.x300.inc viv_ip NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2"
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# post_build($1=Device, $2=Option)
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ifeq ($(TARGET),bin)
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post_build = @\
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mkdir -p $(BUILD_OUTPUT_DIR); \
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echo "Exporting bitstream files..."; \
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cp $(BUILD_BASE_DIR)/build-$(1)_$(2)/x300.bin $(BUILD_OUTPUT_DIR)/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bin; \
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cp $(BUILD_BASE_DIR)/build-$(1)_$(2)/x300.bit $(BUILD_OUTPUT_DIR)/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bit; \
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cp $(ARTIFACT_DIR)/x300.bin $(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).bin; \
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cp $(ARTIFACT_DIR)/x300.bit $(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).bit; \
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echo "Generating LVBITX..."; \
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$(CREATE_LVBITX) --input-bin=$(BUILD_BASE_DIR)/build-$(1)_$(2)/x300.bin --output-lvbitx=$(BUILD_OUTPUT_DIR)/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).lvbitx --device="USRP $(1)" x3x0_base.lvbitx; \
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$(CREATE_LVBITX) --input-bin=$(ARTIFACT_DIR)/x300.bin --output-lvbitx=$(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).lvbitx --device="USRP $(1)" x3x0_base.lvbitx; \
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cp -f x3x0_base.lvbitx $(BUILD_OUTPUT_DIR)/`echo $(1) | tr A-Z a-z`.lvbitx_base; \
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echo "Exporting build report..."; \
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cp $(BUILD_BASE_DIR)/build-$(1)_$(2)/build.rpt $(BUILD_OUTPUT_DIR)/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).rpt; \
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cp $(ARTIFACT_DIR)/build.rpt $(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).rpt; \
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echo "Build DONE ... $(1)_$(2)";
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else
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post_build = @echo "Skipping bitfile export."
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@@ -141,13 +138,13 @@ X300_XA: X300_IP
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clean: ##Clean up all target build outputs.
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@echo "Cleaning targets..."
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@rm -rf $(BUILD_BASE_DIR)/build-X3*_*
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@rm -rf $(BUILD_BASE_DIR)/build-X3*_* $(BUILD_BASE_DIR)/build-x3*
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@rm -rf $(BUILD_OUTPUT_DIR)
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cleanall: ##Clean up all target and ip build outputs.
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@echo "Cleaning targets and IP..."
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@rm -rf build-ip
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@rm -rf $(BUILD_BASE_DIR)/build-X3*_*
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@rm -rf $(BUILD_BASE_DIR)/build-X3*_* $(BUILD_BASE_DIR)/build-x3*
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@rm -rf $(BUILD_OUTPUT_DIR)
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help: ##Show this help message.
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@@ -39,23 +39,15 @@ include $(LIB_DIR)/rfnoc/Makefile.srcs
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include $(LIB_DIR)/axi4s_sv/Makefile.srcs
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include $(LIB_DIR)/rfnoc/xport_sv/Makefile.srcs
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# For sake of convenience, we include the Makefile.srcs for DRAM FIFO, DDC, and
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# DUC, Replay, and of course the radio. Any other block needs to use the
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# RFNOC_OOT_MAKEFILE_SRCS variable (see below).
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include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_axi_ram_fifo/Makefile.srcs
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include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_radio/Makefile.srcs
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include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_ddc/Makefile.srcs
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include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_duc/Makefile.srcs
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include $(LIB_DIR)/rfnoc/blocks/rfnoc_block_replay/Makefile.srcs
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# If out-of-tree modules want to be compiled into this image, then they need to
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# pass in the RFNOC_OOT_MAKEFILE_SRCS as a list of Makefile.srcs files.
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# Those files need to amend the RFNOC_OOT_SRCS variable with a list of actual
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# source files.
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-include $(RFNOC_OOT_MAKEFILE_SRCS)
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IMAGE_CORE ?= $(DEFAULT_RFNOC_IMAGE_CORE_FILE)
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EDGE_FILE ?= $(DEFAULT_EDGE_FILE)
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ifdef ARTIFACT_DIR
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include $(ARTIFACT_DIR)/Makefile.inc
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endif
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##################################################
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# Sources
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@@ -73,8 +65,7 @@ capture_ddrlvds.v \
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gen_ddrlvds.v \
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bus_int.v \
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x300.xdc \
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timing.xdc \
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$(IMAGE_CORE)
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timing.xdc
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ifdef BUILD_10G
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SFP_SERDES_SRCS += $(XGE_SRCS) $(XGE_INTERFACE_SRCS) $(abspath x300_10ge.xdc) $(TEN_GIGE_PHY_SRCS) $(IP_TEN_GIGE_PHY_XCI_SRCS)
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@@ -112,21 +103,20 @@ $(PACKET_PROC_SRCS) $(DSP_SRCS) $(DRAM_SRCS) \
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$(AXI_SRCS) $(CAP_GEN_GENERIC_SRCS) $(IP_XCI_SRCS) $(BD_SRCS) \
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$(RFNOC_SRCS) $(LIB_IP_XCI_SRCS) \
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$(RFNOC_FRAMEWORK_SRCS) \
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$(RFNOC_BLOCK_DUC_SRCS) $(RFNOC_BLOCK_DDC_SRCS) $(RFNOC_BLOCK_RADIO_SRCS) \
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$(RFNOC_BLOCK_AXI_RAM_FIFO_SRCS) \
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$(RFNOC_BLOCK_REPLAY_SRCS) \
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$(RFNOC_OOT_SRCS) \
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$(AXI4S_SV_SRCS) $(RFNOC_XPORT_SV_SRCS) \
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$(RFNOC_IMAGE_CORE_SRCS)
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EDGE_TBL_DEF="RFNOC_EDGE_TBL_FILE=$(call RESOLVE_PATH,$(EDGE_FILE))"
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IMAGE_CORE_DEF="RFNOC_IMAGE_CORE_HDR=$(DEFAULT_RFNOC_IMAGE_CORE_FILE:.v=.vh)"
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# Pass the image core header files required by RFNoC
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# to Vivado as Verilog definitions.
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IMAGE_CORE_HEADER_DEF="RFNOC_IMAGE_CORE_HDR=$(ARTIFACT_DIR)/rfnoc_image_core.vh"
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##################################################
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# Dependency Targets
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##################################################
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.SECONDEXPANSION:
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VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(EDGE_TBL_DEF) $(IMAGE_CORE_DEF)
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VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(IMAGE_CORE_HEADER_DEF) $(RFNOC_IMAGE_CORE_DEFS)
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# DESIGN_SRCS and VERILOG_DEFS must be defined
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bin: .prereqs
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@@ -0,0 +1,72 @@
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# General parameters
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# -----------------------------------------
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schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
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copyright: >- # Copyright information used in file headers
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Copyright 2023 Ettus Research, a National Instruments Brand
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license: >- # License information used in file headers
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SPDX-License-Identifier: LGPL-3.0-or-later
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version: '1.0' # File version
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chdr_width: 64 # Bit width of the CHDR bus for this image
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device: 'x310'
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image_core_name: 'usrp_x300_fpga_HG' # This is used for the bitfile, DTS, and report
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default_target: 'X300_HG'
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inherit:
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- 'yaml_include/x3xx_radio_base.yml'
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# A list of all stream endpoints in design
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# ----------------------------------------
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stream_endpoints:
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ep0: # Stream endpoint name
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buff_size: 32768 # Ingress buffer size for data
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ep1:
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buff_size: 0
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ep2:
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buff_size: 32768
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ep3:
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buff_size: 0
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ep4:
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buff_size: 4096
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ctrl: False
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data: True
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ep5:
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buff_size: 4096
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ctrl: False
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data: True
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# A list of all NoC blocks in design
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# ----------------------------------
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noc_blocks:
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replay0:
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block_desc: 'replay.yml'
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parameters:
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NUM_PORTS: 2
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MEM_DATA_W: 64
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MEM_ADDR_W: 30
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priority: 99 # Make sure they come after the blocks defined in x3xx_radio_base.yml
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# A list of all static connections in design
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# ------------------------------------------
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# Format: A list of connection maps (list of key-value pairs) with the following keys
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# - srcblk = Source block to connect
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# - srcport = Port on the source block to connect
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# - dstblk = Destination block to connect
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# - dstport = Port on the destination block to connect
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connections:
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# Replay Connections
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- { srcblk: ep4, srcport: out0, dstblk: replay0, dstport: in_0 }
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- { srcblk: replay0, srcport: out_0, dstblk: ep4, dstport: in0 }
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- { srcblk: ep5, srcport: out0, dstblk: replay0, dstport: in_1 }
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- { srcblk: replay0, srcport: out_1, dstblk: ep5, dstport: in0 }
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#
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# BSP Connections
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- { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram }
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# A list of all clock domain connections in design
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# ------------------------------------------------
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# Format: A list of connection maps (list of key-value pairs) with the following keys
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# - srcblk = Source block to connect (Always "_device"_)
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# - srcport = Clock domain on the source block to connect
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# - dstblk = Destination block to connect
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# - dstport = Clock domain on the destination block to connect
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clk_domains:
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- { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem }
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@@ -0,0 +1,72 @@
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# General parameters
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# -----------------------------------------
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schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
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copyright: >- # Copyright information used in file headers
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Copyright 2023 Ettus Research, a National Instruments Brand
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license: >- # License information used in file headers
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SPDX-License-Identifier: LGPL-3.0-or-later
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version: '1.0' # File version
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chdr_width: 64 # Bit width of the CHDR bus for this image
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device: 'x310'
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image_core_name: 'usrp_x300_fpga_XG' # This is used for the bitfile, DTS, and report
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default_target: 'X300_XG'
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inherit:
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- 'yaml_include/x3xx_radio_base.yml'
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# A list of all stream endpoints in design
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# ----------------------------------------
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stream_endpoints:
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ep0: # Stream endpoint name
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buff_size: 32768 # Ingress buffer size for data
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ep1:
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buff_size: 0
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ep2:
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buff_size: 32768
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ep3:
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buff_size: 0
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ep4:
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buff_size: 4096
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ctrl: False
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data: True
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ep5:
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buff_size: 4096
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ctrl: False
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data: True
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# A list of all NoC blocks in design
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# ----------------------------------
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noc_blocks:
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replay0:
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block_desc: 'replay.yml'
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parameters:
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NUM_PORTS: 2
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MEM_DATA_W: 64
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MEM_ADDR_W: 30
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priority: 99 # Make sure they come after the blocks defined in x3xx_radio_base.yml
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# A list of all static connections in design
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# ------------------------------------------
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# Format: A list of connection maps (list of key-value pairs) with the following keys
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# - srcblk = Source block to connect
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# - srcport = Port on the source block to connect
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# - dstblk = Destination block to connect
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# - dstport = Port on the destination block to connect
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connections:
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# Replay Connections
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- { srcblk: ep4, srcport: out0, dstblk: replay0, dstport: in_0 }
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- { srcblk: replay0, srcport: out_0, dstblk: ep4, dstport: in0 }
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- { srcblk: ep5, srcport: out0, dstblk: replay0, dstport: in_1 }
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- { srcblk: replay0, srcport: out_1, dstblk: ep5, dstport: in0 }
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#
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# BSP Connections
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- { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram }
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# A list of all clock domain connections in design
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# ------------------------------------------------
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# Format: A list of connection maps (list of key-value pairs) with the following keys
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# - srcblk = Source block to connect (Always "_device"_)
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# - srcport = Clock domain on the source block to connect
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# - dstblk = Destination block to connect
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# - dstport = Clock domain on the destination block to connect
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clk_domains:
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- { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem }
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File diff suppressed because it is too large
Load Diff
@@ -1,19 +0,0 @@
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//
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// Copyright 2023 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Header: rfnoc_image_core.vh (for x300)
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//
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// Description:
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//
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// This is the header file for the RFNoC Image Core.
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//
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// This file was automatically generated by the RFNoC image builder tool.
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// Re-running that tool will overwrite this file!
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//
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// Source: x300_rfnoc_image_core.yml
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//
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`define CHDR_WIDTH 64
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`define RFNOC_PROTOVER { 8'd1, 8'd0 }
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@@ -1,131 +0,0 @@
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# General parameters
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# -----------------------------------------
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schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
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copyright: >- # Copyright information used in file headers
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Copyright 2023 Ettus Research, a National Instruments Brand
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license: >- # License information used in file headers
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SPDX-License-Identifier: LGPL-3.0-or-later
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version: '1.0' # File version
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chdr_width: 64 # Bit width of the CHDR bus for this image
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device: 'x300'
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default_target: 'X300_HG'
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# A list of all stream endpoints in design
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# ----------------------------------------
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stream_endpoints:
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ep0: # Stream endpoint name
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ctrl: True # Endpoint passes control traffic
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data: True # Endpoint passes data traffic
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buff_size: 32768 # Ingress buffer size for data
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ep1:
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ctrl: False
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data: True
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buff_size: 0
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ep2:
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ctrl: False
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data: True
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buff_size: 32768
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ep3:
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ctrl: False
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data: True
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buff_size: 0
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ep4:
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ctrl: False
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data: True
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buff_size: 4096
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ep5:
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ctrl: False
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data: True
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buff_size: 4096
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# A list of all NoC blocks in design
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# ----------------------------------
|
||||
noc_blocks:
|
||||
duc0: # NoC block name
|
||||
block_desc: 'duc.yml' # Block device descriptor file
|
||||
parameters:
|
||||
NUM_PORTS: 1
|
||||
ddc0:
|
||||
block_desc: 'ddc.yml'
|
||||
parameters:
|
||||
NUM_PORTS: 2
|
||||
radio0:
|
||||
block_desc: 'radio.yml'
|
||||
parameters:
|
||||
NUM_PORTS: 2
|
||||
duc1:
|
||||
block_desc: 'duc.yml'
|
||||
parameters:
|
||||
NUM_PORTS: 1
|
||||
ddc1:
|
||||
block_desc: 'ddc.yml'
|
||||
parameters:
|
||||
NUM_PORTS: 2
|
||||
radio1:
|
||||
block_desc: 'radio.yml'
|
||||
parameters:
|
||||
NUM_PORTS: 2
|
||||
replay0:
|
||||
block_desc: 'replay.yml'
|
||||
parameters:
|
||||
NUM_PORTS: 2
|
||||
MEM_ADDR_W: 30
|
||||
|
||||
# A list of all static connections in design
|
||||
# ------------------------------------------
|
||||
# Format: A list of connection maps (list of key-value pairs) with the following keys
|
||||
# - srcblk = Source block to connect
|
||||
# - srcport = Port on the source block to connect
|
||||
# - dstblk = Destination block to connect
|
||||
# - dstport = Port on the destination block to connect
|
||||
connections:
|
||||
# RF A TX
|
||||
- { srcblk: ep0, srcport: out0, dstblk: duc0, dstport: in_0 }
|
||||
- { srcblk: duc0, srcport: out_0, dstblk: radio0, dstport: in_0 }
|
||||
# RF A RX
|
||||
- { srcblk: radio0, srcport: out_0, dstblk: ddc0, dstport: in_0 }
|
||||
- { srcblk: ddc0, srcport: out_0, dstblk: ep0, dstport: in0 }
|
||||
# RF A RX2
|
||||
- { srcblk: radio0, srcport: out_1, dstblk: ddc0, dstport: in_1 }
|
||||
- { srcblk: ddc0, srcport: out_1, dstblk: ep1, dstport: in0 }
|
||||
#
|
||||
# RF B TX
|
||||
- { srcblk: ep2, srcport: out0, dstblk: duc1, dstport: in_0 }
|
||||
- { srcblk: duc1, srcport: out_0, dstblk: radio1, dstport: in_0 }
|
||||
# RF B RX
|
||||
- { srcblk: radio1, srcport: out_0, dstblk: ddc1, dstport: in_0 }
|
||||
- { srcblk: ddc1, srcport: out_0, dstblk: ep2, dstport: in0 }
|
||||
# RF B RX2
|
||||
- { srcblk: radio1, srcport: out_1, dstblk: ddc1, dstport: in_1 }
|
||||
- { srcblk: ddc1, srcport: out_1, dstblk: ep3, dstport: in0 }
|
||||
#
|
||||
# Replay Connections
|
||||
- { srcblk: ep4, srcport: out0, dstblk: replay0, dstport: in_0 }
|
||||
- { srcblk: replay0, srcport: out_0, dstblk: ep4, dstport: in0 }
|
||||
- { srcblk: ep5, srcport: out0, dstblk: replay0, dstport: in_1 }
|
||||
- { srcblk: replay0, srcport: out_1, dstblk: ep5, dstport: in0 }
|
||||
#
|
||||
# BSP Connections
|
||||
- { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 }
|
||||
- { srcblk: radio1, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio1 }
|
||||
- { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram }
|
||||
- { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio }
|
||||
- { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio }
|
||||
- { srcblk: _device_, srcport: time, dstblk: radio0, dstport: time }
|
||||
- { srcblk: _device_, srcport: time, dstblk: radio1, dstport: time }
|
||||
|
||||
# A list of all clock domain connections in design
|
||||
# ------------------------------------------------
|
||||
# Format: A list of connection maps (list of key-value pairs) with the following keys
|
||||
# - srcblk = Source block to connect (Always "_device"_)
|
||||
# - srcport = Clock domain on the source block to connect
|
||||
# - dstblk = Destination block to connect
|
||||
# - dstport = Clock domain on the destination block to connect
|
||||
clk_domains:
|
||||
- { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio }
|
||||
- { srcblk: _device_, srcport: ce, dstblk: ddc0, dstport: ce }
|
||||
- { srcblk: _device_, srcport: ce, dstblk: duc0, dstport: ce }
|
||||
- { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio }
|
||||
- { srcblk: _device_, srcport: ce, dstblk: ddc1, dstport: ce }
|
||||
- { srcblk: _device_, srcport: ce, dstblk: duc1, dstport: ce }
|
||||
- { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem }
|
||||
@@ -1,17 +0,0 @@
|
||||
00000010
|
||||
004001c0
|
||||
01c00240
|
||||
02400200
|
||||
02000040
|
||||
02410201
|
||||
02010080
|
||||
00c00280
|
||||
02800300
|
||||
030002c0
|
||||
02c000c0
|
||||
030102c1
|
||||
02c10100
|
||||
01400340
|
||||
03400140
|
||||
01800341
|
||||
03410180
|
||||
@@ -0,0 +1,72 @@
|
||||
# General parameters
|
||||
# -----------------------------------------
|
||||
schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
|
||||
copyright: >- # Copyright information used in file headers
|
||||
Copyright 2023 Ettus Research, a National Instruments Brand
|
||||
license: >- # License information used in file headers
|
||||
SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
version: '1.0' # File version
|
||||
chdr_width: 64 # Bit width of the CHDR bus for this image
|
||||
device: 'x310'
|
||||
image_core_name: 'usrp_x310_fpga_HG' # This is used for the bitfile, DTS, and report
|
||||
default_target: 'X310_HG'
|
||||
inherit:
|
||||
- 'yaml_include/x3xx_radio_base.yml'
|
||||
|
||||
# A list of all stream endpoints in design
|
||||
# ----------------------------------------
|
||||
stream_endpoints:
|
||||
ep0: # Stream endpoint name
|
||||
buff_size: 65536 # Ingress buffer size for data
|
||||
ep1:
|
||||
buff_size: 0
|
||||
ep2:
|
||||
buff_size: 65536
|
||||
ep3:
|
||||
buff_size: 0
|
||||
ep4:
|
||||
buff_size: 4096
|
||||
ctrl: False
|
||||
data: True
|
||||
ep5:
|
||||
buff_size: 4096
|
||||
ctrl: False
|
||||
data: True
|
||||
|
||||
# A list of all NoC blocks in design
|
||||
# ----------------------------------
|
||||
noc_blocks:
|
||||
replay0:
|
||||
block_desc: 'replay.yml'
|
||||
parameters:
|
||||
NUM_PORTS: 2
|
||||
MEM_DATA_W: 64
|
||||
MEM_ADDR_W: 30
|
||||
priority: 99 # Make sure they come after the blocks defined in x3xx_radio_base.yml
|
||||
|
||||
# A list of all static connections in design
|
||||
# ------------------------------------------
|
||||
# Format: A list of connection maps (list of key-value pairs) with the following keys
|
||||
# - srcblk = Source block to connect
|
||||
# - srcport = Port on the source block to connect
|
||||
# - dstblk = Destination block to connect
|
||||
# - dstport = Port on the destination block to connect
|
||||
connections:
|
||||
# Replay Connections
|
||||
- { srcblk: ep4, srcport: out0, dstblk: replay0, dstport: in_0 }
|
||||
- { srcblk: replay0, srcport: out_0, dstblk: ep4, dstport: in0 }
|
||||
- { srcblk: ep5, srcport: out0, dstblk: replay0, dstport: in_1 }
|
||||
- { srcblk: replay0, srcport: out_1, dstblk: ep5, dstport: in0 }
|
||||
#
|
||||
# BSP Connections
|
||||
- { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram }
|
||||
|
||||
# A list of all clock domain connections in design
|
||||
# ------------------------------------------------
|
||||
# Format: A list of connection maps (list of key-value pairs) with the following keys
|
||||
# - srcblk = Source block to connect (Always "_device"_)
|
||||
# - srcport = Clock domain on the source block to connect
|
||||
# - dstblk = Destination block to connect
|
||||
# - dstport = Clock domain on the destination block to connect
|
||||
clk_domains:
|
||||
- { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem }
|
||||
@@ -0,0 +1,72 @@
|
||||
# General parameters
|
||||
# -----------------------------------------
|
||||
schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
|
||||
copyright: >- # Copyright information used in file headers
|
||||
Copyright 2023 Ettus Research, a National Instruments Brand
|
||||
license: >- # License information used in file headers
|
||||
SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
version: '1.0' # File version
|
||||
chdr_width: 64 # Bit width of the CHDR bus for this image
|
||||
device: 'x310'
|
||||
image_core_name: 'usrp_x310_fpga_XG' # This is used for the bitfile, DTS, and report
|
||||
default_target: 'X310_XG'
|
||||
inherit:
|
||||
- 'yaml_include/x3xx_radio_base.yml'
|
||||
|
||||
# A list of all stream endpoints in design
|
||||
# ----------------------------------------
|
||||
stream_endpoints:
|
||||
ep0: # Stream endpoint name
|
||||
buff_size: 65536 # Ingress buffer size for data
|
||||
ep1:
|
||||
buff_size: 0
|
||||
ep2:
|
||||
buff_size: 65536
|
||||
ep3:
|
||||
buff_size: 0
|
||||
ep4:
|
||||
buff_size: 4096
|
||||
ctrl: False
|
||||
data: True
|
||||
ep5:
|
||||
buff_size: 4096
|
||||
ctrl: False
|
||||
data: True
|
||||
|
||||
# A list of all NoC blocks in design
|
||||
# ----------------------------------
|
||||
noc_blocks:
|
||||
replay0:
|
||||
block_desc: 'replay.yml'
|
||||
parameters:
|
||||
NUM_PORTS: 2
|
||||
MEM_DATA_W: 64
|
||||
MEM_ADDR_W: 30
|
||||
priority: 99 # Make sure they come after the blocks defined in x3xx_radio_base.yml
|
||||
|
||||
# A list of all static connections in design
|
||||
# ------------------------------------------
|
||||
# Format: A list of connection maps (list of key-value pairs) with the following keys
|
||||
# - srcblk = Source block to connect
|
||||
# - srcport = Port on the source block to connect
|
||||
# - dstblk = Destination block to connect
|
||||
# - dstport = Port on the destination block to connect
|
||||
connections:
|
||||
# Replay Connections
|
||||
- { srcblk: ep4, srcport: out0, dstblk: replay0, dstport: in_0 }
|
||||
- { srcblk: replay0, srcport: out_0, dstblk: ep4, dstport: in0 }
|
||||
- { srcblk: ep5, srcport: out0, dstblk: replay0, dstport: in_1 }
|
||||
- { srcblk: replay0, srcport: out_1, dstblk: ep5, dstport: in0 }
|
||||
#
|
||||
# BSP Connections
|
||||
- { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram }
|
||||
|
||||
# A list of all clock domain connections in design
|
||||
# ------------------------------------------------
|
||||
# Format: A list of connection maps (list of key-value pairs) with the following keys
|
||||
# - srcblk = Source block to connect (Always "_device"_)
|
||||
# - srcport = Clock domain on the source block to connect
|
||||
# - dstblk = Destination block to connect
|
||||
# - dstport = Clock domain on the destination block to connect
|
||||
clk_domains:
|
||||
- { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem }
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,19 +0,0 @@
|
||||
//
|
||||
// Copyright 2023 Ettus Research, a National Instruments Brand
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Header: rfnoc_image_core.vh (for x310)
|
||||
//
|
||||
// Description:
|
||||
//
|
||||
// This is the header file for the RFNoC Image Core.
|
||||
//
|
||||
// This file was automatically generated by the RFNoC image builder tool.
|
||||
// Re-running that tool will overwrite this file!
|
||||
//
|
||||
// Source: x310_rfnoc_image_core.yml
|
||||
//
|
||||
|
||||
`define CHDR_WIDTH 64
|
||||
`define RFNOC_PROTOVER { 8'd1, 8'd0 }
|
||||
@@ -1,17 +0,0 @@
|
||||
00000010
|
||||
004001c0
|
||||
01c00240
|
||||
02400200
|
||||
02000040
|
||||
02410201
|
||||
02010080
|
||||
00c00280
|
||||
02800300
|
||||
030002c0
|
||||
02c000c0
|
||||
030102c1
|
||||
02c10100
|
||||
01400340
|
||||
03400140
|
||||
01800341
|
||||
03410180
|
||||
@@ -7,8 +7,6 @@ license: >- # License information used in file heade
|
||||
SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
version: '1.0' # File version
|
||||
chdr_width: 64 # Bit width of the CHDR bus for this image
|
||||
device: 'x310'
|
||||
default_target: 'X310_HG'
|
||||
|
||||
# A list of all stream endpoints in design
|
||||
# ----------------------------------------
|
||||
@@ -16,7 +14,7 @@ stream_endpoints:
|
||||
ep0: # Stream endpoint name
|
||||
ctrl: True # Endpoint passes control traffic
|
||||
data: True # Endpoint passes data traffic
|
||||
buff_size: 65536 # Ingress buffer size for data
|
||||
buff_size: 32768 # Ingress buffer size for data
|
||||
ep1:
|
||||
ctrl: False
|
||||
data: True
|
||||
@@ -24,19 +22,11 @@ stream_endpoints:
|
||||
ep2:
|
||||
ctrl: False
|
||||
data: True
|
||||
buff_size: 65536
|
||||
buff_size: 32768
|
||||
ep3:
|
||||
ctrl: False
|
||||
data: True
|
||||
buff_size: 0
|
||||
ep4:
|
||||
ctrl: False
|
||||
data: True
|
||||
buff_size: 4096
|
||||
ep5:
|
||||
ctrl: False
|
||||
data: True
|
||||
buff_size: 4096
|
||||
|
||||
# A list of all NoC blocks in design
|
||||
# ----------------------------------
|
||||
@@ -65,12 +55,6 @@ noc_blocks:
|
||||
block_desc: 'radio.yml'
|
||||
parameters:
|
||||
NUM_PORTS: 2
|
||||
replay0:
|
||||
block_desc: 'replay.yml'
|
||||
parameters:
|
||||
NUM_PORTS: 2
|
||||
MEM_DATA_W: 64
|
||||
MEM_ADDR_W: 30
|
||||
|
||||
# A list of all static connections in design
|
||||
# ------------------------------------------
|
||||
@@ -100,16 +84,9 @@ connections:
|
||||
- { srcblk: radio1, srcport: out_1, dstblk: ddc1, dstport: in_1 }
|
||||
- { srcblk: ddc1, srcport: out_1, dstblk: ep3, dstport: in0 }
|
||||
#
|
||||
# Replay Connections
|
||||
- { srcblk: ep4, srcport: out0, dstblk: replay0, dstport: in_0 }
|
||||
- { srcblk: replay0, srcport: out_0, dstblk: ep4, dstport: in0 }
|
||||
- { srcblk: ep5, srcport: out0, dstblk: replay0, dstport: in_1 }
|
||||
- { srcblk: replay0, srcport: out_1, dstblk: ep5, dstport: in0 }
|
||||
#
|
||||
# BSP Connections
|
||||
- { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 }
|
||||
- { srcblk: radio1, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio1 }
|
||||
- { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram }
|
||||
- { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio }
|
||||
- { srcblk: _device_, srcport: radio1, dstblk: radio1, dstport: radio }
|
||||
- { srcblk: _device_, srcport: time, dstblk: radio0, dstport: time }
|
||||
@@ -129,4 +106,4 @@ clk_domains:
|
||||
- { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio }
|
||||
- { srcblk: _device_, srcport: ce, dstblk: ddc1, dstport: ce }
|
||||
- { srcblk: _device_, srcport: ce, dstblk: duc1, dstport: ce }
|
||||
- { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem }
|
||||
|
||||
Reference in New Issue
Block a user