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fpga: Updating FPGA code for UHD-3.7.2-rc1

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Original-commit: b63507efb3cf1a8fa20794c452d57028e18da182
This commit is contained in:
Ben Hilburn
2014-07-22 15:49:02 -07:00
parent 5a525c84f5
commit 85ad83d8d3
58 changed files with 3179 additions and 3154 deletions
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top/x300/gen_ddrlvds.v
+4 -1
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@@ -31,6 +31,8 @@ module gen_ddrlvds
reg rising_edge;
wire [15:0] i_and_q_2x;
reg sync_2x;
reg sync_dacs_reg;
genvar z;
@@ -55,6 +57,7 @@ module gen_ddrlvds
begin
i_reg <= i;
q_reg <= q;
sync_dacs_reg <= sync_dacs;
end
always @(posedge tx_clk_2x)
@@ -67,7 +70,7 @@ module gen_ddrlvds
// To sync multiple AD9146 DAC's an extended assertion of FRAME is required,
// when sync flag set, squash one rising_edge assertion which causes a 3 word assertion of FRAME,
// also reset sync flag. "sync_dacs" comes from 1x clk and pulse lasts 2 2x clock cycles...this is accounted for.
sync_2x <= (phase_eq_phase2x && sync_2x) ? 1'b0 /*RESET */ : (sync_dacs) ? 1'b1 /* SET */ : sync_2x /* HOLD */;
sync_2x <= (phase_eq_phase2x && sync_2x) ? 1'b0 /*RESET */ : (sync_dacs_reg) ? 1'b1 /* SET */ : sync_2x /* HOLD */;
rising_edge <= (phase_eq_phase2x && ~sync_2x);
phase_2x <= phase;
end