fpga: Updating FPGA code for UHD-3.7.2-rc1

Original-commit: b63507efb3cf1a8fa20794c452d57028e18da182
2014-07-22 15:49:02 -07:00
parent 5a525c84f5
commit 85ad83d8d3
58 changed files with 3179 additions and 3154 deletions
@@ -1,6 +1,6 @@
 SET busformat = BusFormatAngleBracketNotRipped
 SET designentry = Verilog
-SET device = xc7k325t
+SET device = xc7k410t
 SET devicefamily = kintex7
 SET flowvendor = Other
 SET package = ffg900