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fpga: Updating FPGA code for UHD-3.7.2-rc1

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Original-commit: b63507efb3cf1a8fa20794c452d57028e18da182
This commit is contained in:
Ben Hilburn
2014-07-22 15:49:02 -07:00
parent 5a525c84f5
commit 85ad83d8d3
58 changed files with 3179 additions and 3154 deletions
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top/b200/coregen/chipscope_icon.gise
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<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
top/b200/coregen/chipscope_icon.xise
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@@ -9,10 +9,10 @@
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
<version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="chipscope_icon.ngc" xil_pn:type="FILE_NGC">
top/b200/coregen/chipscope_ila_128.gise
+1 -1
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@@ -15,7 +15,7 @@
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
top/b200/coregen/chipscope_ila_128.xise
+2 -2
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@@ -9,10 +9,10 @@
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
<version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="chipscope_ila_128.ngc" xil_pn:type="FILE_NGC">
top/b200/coregen/chipscope_ila_256.gise
+1 -1
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@@ -15,7 +15,7 @@
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
top/b200/coregen/chipscope_ila_256.xise
+2 -2
View File
@@ -9,10 +9,10 @@
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
<version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="chipscope_ila_256.ngc" xil_pn:type="FILE_NGC">
top/b200/coregen/chipscope_ila_32.gise
+1 -1
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@@ -15,7 +15,7 @@
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
top/b200/coregen/chipscope_ila_32.xise
+2 -2
View File
@@ -9,10 +9,10 @@
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
<version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="chipscope_ila_32.ngc" xil_pn:type="FILE_NGC">
top/b200/coregen/fifo_4k_2clk.gise
+1 -1
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@@ -15,7 +15,7 @@
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
top/b200/coregen/fifo_4k_2clk.xise
+2 -2
View File
@@ -9,10 +9,10 @@
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
<version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="fifo_4k_2clk.ngc" xil_pn:type="FILE_NGC">
top/b200/coregen/fifo_short_2clk.gise
+1 -1
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@@ -15,7 +15,7 @@
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
top/b200/coregen/fifo_short_2clk.xise
+2 -2
View File
@@ -9,10 +9,10 @@
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
<version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="fifo_short_2clk.ngc" xil_pn:type="FILE_NGC">