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fpga: Updating FPGA code for UHD-3.7.2-rc1

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Original-commit: b63507efb3cf1a8fa20794c452d57028e18da182
This commit is contained in:
Ben Hilburn
2014-07-22 15:49:02 -07:00
parent 5a525c84f5
commit 85ad83d8d3
58 changed files with 3179 additions and 3154 deletions
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top/b200/b200_core.v
+19 -6
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@@ -1,5 +1,5 @@
//
// Copyright 2013 Ettus Research LLC
// Copyright 2013-14 Ettus Research LLC
//
@@ -78,11 +78,24 @@ module b200_core
/*******************************************************************
* PPS Timing stuff
******************************************************************/
reg [1:0] int_pps_del, ext_pps_del;
// Generate an internal PPS signal
wire int_pps;
pps_generator #(.CLK_FREQ(100000000)) pps_gen
(.clk(bus_clk), .pps(int_pps));
// Flop PPS signals into radio clock domain
reg [1:0] gpsdo_pps_del, ext_pps_del, int_pps_del;
always @(posedge radio_clk) ext_pps_del[1:0] <= {ext_pps_del[0], pps_ext};
always @(posedge radio_clk) int_pps_del[1:0] <= {int_pps_del[0], pps_int};
wire pps_select;
wire pps = pps_select? ext_pps_del[1] : int_pps_del[1];
always @(posedge radio_clk) gpsdo_pps_del[1:0] <= {gpsdo_pps_del[0], pps_int};
always @(posedge radio_clk) int_pps_del[1:0] <= {int_pps_del[0], int_pps};
// PPS mux
wire [1:0] pps_select;
wire pps = (pps_select == 2'b00)? gpsdo_pps_del[1] :
(pps_select == 2'b01)? ext_pps_del[1] :
(pps_select == 2'b10)? int_pps_del[1] :
1'b0;
/*******************************************************************
* Response mux Routing logic
@@ -189,7 +202,7 @@ module b200_core
(.clk(bus_clk), .rst(1'b0/*keep*/), .strobe(set_stb), .addr(set_addr), .in(set_data),
.out(gpsdo_st), .changed());
setting_reg #(.my_addr(SR_CORE_PPS_SEL), .awidth(8), .width(1)) sr_pps_sel
setting_reg #(.my_addr(SR_CORE_PPS_SEL), .awidth(8), .width(2)) sr_pps_sel
(.clk(bus_clk), .rst(bus_rst), .strobe(set_stb), .addr(set_addr), .in(set_data),
.out(pps_select), .changed());
top/b200/coregen/chipscope_icon.gise
+1 -1
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@@ -15,7 +15,7 @@
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
top/b200/coregen/chipscope_icon.xise
+2 -2
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@@ -9,10 +9,10 @@
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
<version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="chipscope_icon.ngc" xil_pn:type="FILE_NGC">
top/b200/coregen/chipscope_ila_128.gise
+1 -1
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@@ -15,7 +15,7 @@
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
top/b200/coregen/chipscope_ila_128.xise
+2 -2
View File
@@ -9,10 +9,10 @@
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
<version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="chipscope_ila_128.ngc" xil_pn:type="FILE_NGC">
top/b200/coregen/chipscope_ila_256.gise
+1 -1
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@@ -15,7 +15,7 @@
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
top/b200/coregen/chipscope_ila_256.xise
+2 -2
View File
@@ -9,10 +9,10 @@
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
<version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="chipscope_ila_256.ngc" xil_pn:type="FILE_NGC">
top/b200/coregen/chipscope_ila_32.gise
+1 -1
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@@ -15,7 +15,7 @@
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
top/b200/coregen/chipscope_ila_32.xise
+2 -2
View File
@@ -9,10 +9,10 @@
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
<version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="chipscope_ila_32.ngc" xil_pn:type="FILE_NGC">
top/b200/coregen/fifo_4k_2clk.gise
+1 -1
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@@ -15,7 +15,7 @@
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
top/b200/coregen/fifo_4k_2clk.xise
+2 -2
View File
@@ -9,10 +9,10 @@
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
<version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="fifo_4k_2clk.ngc" xil_pn:type="FILE_NGC">
top/b200/coregen/fifo_short_2clk.gise
+1 -1
View File
@@ -15,7 +15,7 @@
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
top/b200/coregen/fifo_short_2clk.xise
+2 -2
View File
@@ -9,10 +9,10 @@
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
<version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="fifo_short_2clk.ngc" xil_pn:type="FILE_NGC">