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fpga: Updating FPGA code for UHD-3.7.2-rc1

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Original-commit: b63507efb3cf1a8fa20794c452d57028e18da182
This commit is contained in:
Ben Hilburn
2014-07-22 15:49:02 -07:00
parent 5a525c84f5
commit 85ad83d8d3
58 changed files with 3179 additions and 3154 deletions
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lib/timing/timekeeper.v
+15 -9
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@@ -1,5 +1,5 @@
//
// Copyright 2013 Ettus Research LLC
// Copyright 2013-2014 Ettus Research LLC
//
@@ -19,11 +19,11 @@ module timekeeper
setting_reg #(.my_addr(BASE), .width()) sr_time_hi
(.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
.out(time_at_next_event[63:32]), .changed());
setting_reg #(.my_addr(BASE+1), .width()) sr_time_lo
(.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
.out(time_at_next_event[31:0]), .changed());
setting_reg #(.my_addr(BASE+2), .width(2)) sr_ctrl
(.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
.out({set_time_pps, set_time_now}), .changed(cmd_trigger));
@@ -37,12 +37,6 @@ module timekeeper
wire pps_edge = !pps_del2 & pps_del;
//////////////////////////////////////////////////////////////////////////
// track the time at last pps so host can detect the pps
//////////////////////////////////////////////////////////////////////////
always @(posedge clk)
if(pps_edge) vita_time_lastpps <= vita_time;
//////////////////////////////////////////////////////////////////////////
// arm the trigger to latch a new time when the ctrl register is written
//////////////////////////////////////////////////////////////////////////
@@ -65,4 +59,16 @@ module timekeeper
else
vita_time <= vita_time + 64'h1;
//////////////////////////////////////////////////////////////////////////
// track the time at last pps so host can detect the pps
//////////////////////////////////////////////////////////////////////////
always @(posedge clk)
if(reset)
vita_time_lastpps <= 64'h0;
else if(pps_edge)
if(time_event)
vita_time_lastpps <= time_at_next_event;
else
vita_time_lastpps <= vita_time + 64'h1;
endmodule // timekeeper