fpga: Updating FPGA code for UHD-3.7.2-rc1

Original-commit: b63507efb3cf1a8fa20794c452d57028e18da182
2014-07-22 15:49:02 -07:00
parent 5a525c84f5
commit 85ad83d8d3
58 changed files with 3179 additions and 3154 deletions
@@ -0,0 +1,22 @@
+//
+// Copyright 2014 Ettus Research LLC
+//
+
+module pps_generator
+    #(parameter CLK_FREQ=0, DUTY=25)
+    (input clk, input reset, output pps);
+
+    reg[31:0] count;
+
+    always @(posedge clk) begin
+        if (reset) begin
+            count <= 32'b1;
+        end else if (count >= CLK_FREQ) begin
+            count <= 32'b1;
+        end else begin
+            count <= count + 1'b1;
+        end
+    end
+
+    assign pps = (count < CLK_FREQ * DUTY / 100);
+endmodule //pps_generator