miegl/b210-k7-fpga
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

fpga: Updating FPGA code for UHD-3.7.2-rc1

Browse Source 
Original-commit: b63507efb3cf1a8fa20794c452d57028e18da182
This commit is contained in:
Ben Hilburn
2014-07-22 15:49:02 -07:00
parent 5a525c84f5
commit 85ad83d8d3
58 changed files with 3179 additions and 3154 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/timing/Makefile.srcs
+1
View File
@@ -8,4 +8,5 @@
TIMING_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/timing/, \
time_compare.v \
timekeeper.v \
pps.v\
))