fpga: Updating FPGA code for UHD-3.7.2-rc1

Original-commit: b63507efb3cf1a8fa20794c452d57028e18da182

lib/timing/Makefile.srcs

@@ -8,4 +8,5 @@
 TIMING_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/timing/, \
 time_compare.v \
 timekeeper.v \
+pps.v\
 ))

lib/timing/pps.v

@@ -0,0 +1,22 @@
+//
+// Copyright 2014 Ettus Research LLC
+//
+
+module pps_generator
+    #(parameter CLK_FREQ=0, DUTY=25)
+    (input clk, input reset, output pps);
+
+    reg[31:0] count;
+
+    always @(posedge clk) begin
+        if (reset) begin
+            count <= 32'b1;
+        end else if (count >= CLK_FREQ) begin
+            count <= 32'b1;
+        end else begin
+            count <= count + 1'b1;
+        end
+    end
+
+    assign pps = (count < CLK_FREQ * DUTY / 100);
+endmodule //pps_generator

lib/timing/timekeeper.v

@@ -1,5 +1,5 @@
 //
-// Copyright 2013 Ettus Research LLC
+// Copyright 2013-2014 Ettus Research LLC
 //
 
 
@@ -19,11 +19,11 @@ module timekeeper
    setting_reg #(.my_addr(BASE), .width()) sr_time_hi
      (.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
       .out(time_at_next_event[63:32]), .changed());
-   
+
    setting_reg #(.my_addr(BASE+1), .width()) sr_time_lo
      (.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
       .out(time_at_next_event[31:0]), .changed());
-   
+
    setting_reg #(.my_addr(BASE+2), .width(2)) sr_ctrl
      (.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
       .out({set_time_pps, set_time_now}), .changed(cmd_trigger));
@@ -37,12 +37,6 @@ module timekeeper
 
    wire pps_edge = !pps_del2 & pps_del;
 
-   //////////////////////////////////////////////////////////////////////////
-   // track the time at last pps so host can detect the pps
-   //////////////////////////////////////////////////////////////////////////
-   always @(posedge clk)
-     if(pps_edge) vita_time_lastpps <= vita_time;
-
    //////////////////////////////////////////////////////////////////////////
    // arm the trigger to latch a new time when the ctrl register is written
    //////////////////////////////////////////////////////////////////////////
@@ -65,4 +59,16 @@ module timekeeper
      else
        vita_time <= vita_time + 64'h1;
 
+   //////////////////////////////////////////////////////////////////////////
+   // track the time at last pps so host can detect the pps
+   //////////////////////////////////////////////////////////////////////////
+   always @(posedge clk)
+     if(reset)
+       vita_time_lastpps <= 64'h0;
+     else if(pps_edge)
+       if(time_event)
+         vita_time_lastpps <= time_at_next_event;
+       else
+         vita_time_lastpps <= vita_time + 64'h1;
+
 endmodule // timekeeper