fpga: Updating FPGA code for UHD-3.7.2-rc1

Original-commit: b63507efb3cf1a8fa20794c452d57028e18da182

lib/dsp/ddc_chain.v

@@ -1,5 +1,5 @@
 //
-// Copyright 2011-2013 Ettus Research LLC
+// Copyright 2011-2014 Ettus Research LLC
 //
 
 
@@ -37,7 +37,7 @@ module ddc_chain
    wire [WIDTH-1:0] i_cic, q_cic;
    wire [WIDTH-1:0] i_hb1, q_hb1;
    wire [WIDTH-1:0] i_hb2, q_hb2;
-   
+
    wire        strobe_cic, strobe_hb1, strobe_hb2;
    wire        enable_hb1, enable_hb2;
    wire [7:0]  cic_decim_rate;
@@ -45,7 +45,9 @@ module ddc_chain
    reg [WIDTH-1:0]  rx_fe_i_mux, rx_fe_q_mux;
    wire        realmode;
    wire        swap_iq;
-   
+   wire        invert_i;
+   wire        invert_q;
+
    setting_reg #(.my_addr(BASE+0)) sr_0
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(phase_inc),.changed());
@@ -58,22 +60,22 @@ module ddc_chain
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out({enable_hb1, enable_hb2, cic_decim_rate}),.changed());
 
-   setting_reg #(.my_addr(BASE+3), .width(2)) sr_3
+   setting_reg #(.my_addr(BASE+3), .width(4)) sr_3
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
-      .in(set_data),.out({realmode,swap_iq}),.changed());
+      .in(set_data),.out({invert_i,inver_q,realmode,swap_iq}),.changed());
 
    // MUX so we can do realmode signals on either input
-   
+
    always @(posedge clk)
      if(swap_iq)
        begin
-	  rx_fe_i_mux <= rx_fe_q;
-	  rx_fe_q_mux <= realmode ? 0 : rx_fe_i;
+	  rx_fe_i_mux <= invert_i ? ~rx_fe_q + 1 : rx_fe_q;
+	  rx_fe_q_mux <= realmode ? 0 : invert_q ? ~rx_fe_i + 1 : rx_fe_i;
        end
      else
        begin
-	  rx_fe_i_mux <= rx_fe_i;
-	  rx_fe_q_mux <= realmode ? 0 : rx_fe_q;
+	  rx_fe_i_mux <= invert_i ? ~rx_fe_i + 1 : rx_fe_i;
+	  rx_fe_q_mux <= realmode ? 0 : invert_i ? ~rx_fe_q + 1 : rx_fe_q;
        end
 
    // NCO
@@ -109,7 +111,7 @@ module ddc_chain
      decim_i (.clock(clk),.reset(rst),.enable(run),
 	      .rate(cic_decim_rate),.strobe_in(1'b1),.strobe_out(strobe_cic),
 	      .signal_in(i_cordic_clip),.signal_out(i_cic));
-   
+
    cic_decim #(.bw(WIDTH))
      decim_q (.clock(clk),.reset(rst),.enable(run),
 	      .rate(cic_decim_rate),.strobe_in(1'b1),.strobe_out(strobe_cic),
@@ -119,7 +121,7 @@ module ddc_chain
    small_hb_dec #(.WIDTH(WIDTH)) small_hb_i
      (.clk(clk),.rst(rst),.bypass(~enable_hb1),.run(run),
       .stb_in(strobe_cic),.data_in(i_cic),.stb_out(strobe_hb1),.data_out(i_hb1));
-   
+
    small_hb_dec #(.WIDTH(WIDTH)) small_hb_q
      (.clk(clk),.rst(rst),.bypass(~enable_hb1),.run(run),
       .stb_in(strobe_cic),.data_in(q_cic),.stb_out(),.data_out(q_hb1));

lib/timing/Makefile.srcs

@@ -8,4 +8,5 @@
 TIMING_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/timing/, \
 time_compare.v \
 timekeeper.v \
+pps.v\
 ))

lib/timing/pps.v

@@ -0,0 +1,22 @@
+//
+// Copyright 2014 Ettus Research LLC
+//
+
+module pps_generator
+    #(parameter CLK_FREQ=0, DUTY=25)
+    (input clk, input reset, output pps);
+
+    reg[31:0] count;
+
+    always @(posedge clk) begin
+        if (reset) begin
+            count <= 32'b1;
+        end else if (count >= CLK_FREQ) begin
+            count <= 32'b1;
+        end else begin
+            count <= count + 1'b1;
+        end
+    end
+
+    assign pps = (count < CLK_FREQ * DUTY / 100);
+endmodule //pps_generator

lib/timing/timekeeper.v

@@ -1,5 +1,5 @@
 //
-// Copyright 2013 Ettus Research LLC
+// Copyright 2013-2014 Ettus Research LLC
 //
 
 
@@ -19,11 +19,11 @@ module timekeeper
    setting_reg #(.my_addr(BASE), .width()) sr_time_hi
      (.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
       .out(time_at_next_event[63:32]), .changed());
-   
+
    setting_reg #(.my_addr(BASE+1), .width()) sr_time_lo
      (.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
       .out(time_at_next_event[31:0]), .changed());
-   
+
    setting_reg #(.my_addr(BASE+2), .width(2)) sr_ctrl
      (.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
       .out({set_time_pps, set_time_now}), .changed(cmd_trigger));
@@ -37,12 +37,6 @@ module timekeeper
 
    wire pps_edge = !pps_del2 & pps_del;
 
-   //////////////////////////////////////////////////////////////////////////
-   // track the time at last pps so host can detect the pps
-   //////////////////////////////////////////////////////////////////////////
-   always @(posedge clk)
-     if(pps_edge) vita_time_lastpps <= vita_time;
-
    //////////////////////////////////////////////////////////////////////////
    // arm the trigger to latch a new time when the ctrl register is written
    //////////////////////////////////////////////////////////////////////////
@@ -65,4 +59,16 @@ module timekeeper
      else
        vita_time <= vita_time + 64'h1;
 
+   //////////////////////////////////////////////////////////////////////////
+   // track the time at last pps so host can detect the pps
+   //////////////////////////////////////////////////////////////////////////
+   always @(posedge clk)
+     if(reset)
+       vita_time_lastpps <= 64'h0;
+     else if(pps_edge)
+       if(time_event)
+         vita_time_lastpps <= time_at_next_event;
+       else
+         vita_time_lastpps <= vita_time + 64'h1;
+
 endmodule // timekeeper