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fpga: Update makefiles to allow parallel FPGA builds

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This adds the ability to do IP generation and FPGA builds using the
--jobs (-j) option with Make. For example, rather than generating each
IP one after another, you can generate up to N at a time using N Vivado
instances. This greatly reduces the IP generation time. Similarly,
parallel jobs can be used to easily build different FPGA variants
simultaneously.

Because FPGA builds can consume a lot of memory, care must be taken to
ensure that the number of jobs is not too high for the amount of memory
available.

New IP make targets were added for each USRP so that IP can be built
separately from the FPGA. The IP targets are now a dependency on each
FPGA target.

For example, you can generate the IP for X310 using 4 parallel jobs
using the following command:

  make -j4 X310_IP

Or, build two X310 bitstreams simultaneously:

  make -j2 X310_XG X310_HG


Original-commit: 4b03e237a96ee277eefff257d65b08708c38662c
This commit is contained in:
Wade Fife
2022-08-16 10:16:22 -05:00
parent 50bf9c3ae5
commit 81bb2ae28f
100 changed files with 608 additions and 224 deletions
Download Patch File Download Diff File Expand all files Collapse all files
top/x400/Makefile
+18 -20
View File
@@ -84,8 +84,9 @@ ifndef TARGET
endif
TOP ?= x4xx
# vivado_build($1=Device, $2=Definitions)
# vivado_build($1=Device, $2=Definitions, $3=Defaults)
vivado_build = make -f Makefile.x4xx.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" $3
vivado_ip = make -f Makefile.x4xx.inc viv_ip NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" $3
# vivado_build($1=Device, $2=Option)
ifeq ($(TARGET),bin)
@@ -100,9 +101,6 @@ else
post_build = @echo "Skipping bitfile export."
endif
# vivado_ip($1=Device, $2=Definitions)
vivado_ip = make -f Makefile.x4xx.inc viv_ip NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2"
##
##Available Targets
##------------|-----------|-----------------|-----------------|------------
@@ -121,47 +119,47 @@ vivado_ip = make -f Makefile.x4xx.inc viv_ip NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID
##X410_CG_400 | 400 MHz | 100 GbE | 100 GbE | None
##* Note: Not all targets are shipped with UHD
X410_X1_100: build/usrp_x410_fpga_X1_100.dts
X410_X1_100: X410_IP build/usrp_x410_fpga_X1_100.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_100_DEFAULTS))
$(call post_build,X410,X1_100)
X410_XG_100: build/usrp_x410_fpga_XG_100.dts
X410_XG_100: X410_IP build/usrp_x410_fpga_XG_100.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_100_DEFAULTS))
$(call post_build,X410,XG_100)
X410_X4_100: build/usrp_x410_fpga_X4_100.dts
X410_X4_100: X410_IP build/usrp_x410_fpga_X4_100.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_100_DEFAULTS))
$(call post_build,X410,X4_100)
X410_X1_200: build/usrp_x410_fpga_X1_200.dts
X410_X1_200: X410_IP build/usrp_x410_fpga_X1_200.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS))
$(call post_build,X410,X1_200)
X410_XG_200: build/usrp_x410_fpga_XG_200.dts
X410_XG_200: X410_IP build/usrp_x410_fpga_XG_200.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS))
$(call post_build,X410,XG_200)
X410_X4_200: build/usrp_x410_fpga_X4_200.dts
X410_X4_200: X410_IP build/usrp_x410_fpga_X4_200.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS))
$(call post_build,X410,X4_200)
X410_X1_400: build/usrp_x410_fpga_X1_400.dts
X410_X1_400: X410_IP build/usrp_x410_fpga_X1_400.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_128_DEFAULTS))
$(call post_build,X410,X1_400)
X410_XG_400: build/usrp_x410_fpga_XG_400.dts
X410_XG_400: X410_IP build/usrp_x410_fpga_XG_400.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_128_DEFAULTS))
$(call post_build,X410,XG_400)
X410_X4_400: build/usrp_x410_fpga_X4_400.dts
X410_X4_400: X410_IP build/usrp_x410_fpga_X4_400.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_128_DEFAULTS))
$(call post_build,X410,X4_400)
X410_C1_400: build/usrp_x410_fpga_C1_400.dts
X410_C1_400: X410_IP build/usrp_x410_fpga_C1_400.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_DEFAULTS))
$(call post_build,X410,C1_400)
X410_CG_400: build/usrp_x410_fpga_CG_400.dts
X410_CG_400: X410_IP build/usrp_x410_fpga_CG_400.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_DEFAULTS))
$(call post_build,X410,CG_400)
@@ -175,19 +173,19 @@ X410_CG_400: build/usrp_x410_fpga_CG_400.dts
##X410_X4C_200 | 200 | 4 x 10 GbE | 100GbE | None
##X410_C1_200 | 200 | 100 GbE | None | 64b x 4 Ch
X410_X4C_100: build/usrp_x410_fpga_X4C_100.dts
X410_X4C_100: X410_IP build/usrp_x410_fpga_X4C_100.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_100_DEFAULTS))
$(call post_build,X410,X4C_100)
X410_C1_100: build/usrp_x410_fpga_CG_100.dts
X410_C1_100: X410_IP build/usrp_x410_fpga_CG_100.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_100_DEFAULTS))
$(call post_build,X410,CG_100)
X410_C1_200: build/usrp_x410_fpga_CG_200.dts
X410_C1_200: X410_IP build/usrp_x410_fpga_CG_200.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS))
$(call post_build,X410,CG_200)
X410_X4C_200: build/usrp_x410_fpga_X4C_200.dts
X410_X4C_200: X410_IP build/usrp_x410_fpga_X4C_200.dts
$(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS))
$(call post_build,X410,X4C_200)
@@ -200,7 +198,7 @@ X410_X4C_200: build/usrp_x410_fpga_X4C_200.dts
all: X410_X4_200 X410_CG_400 ##(Default targets)
X410_IP: ##Build IP only.
$(call vivado_ip,X410,$(DEFS) X410=1)
+$(call vivado_ip,X410,$(DEFS) X410=1)
build/%.dts: dts/*.dts dts/*.dtsi
-mkdir -p build