miegl/b210-k7-fpga
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

fpga: Update makefiles to allow parallel FPGA builds

Browse Source 
This adds the ability to do IP generation and FPGA builds using the
--jobs (-j) option with Make. For example, rather than generating each
IP one after another, you can generate up to N at a time using N Vivado
instances. This greatly reduces the IP generation time. Similarly,
parallel jobs can be used to easily build different FPGA variants
simultaneously.

Because FPGA builds can consume a lot of memory, care must be taken to
ensure that the number of jobs is not too high for the amount of memory
available.

New IP make targets were added for each USRP so that IP can be built
separately from the FPGA. The IP targets are now a dependency on each
FPGA target.

For example, you can generate the IP for X310 using 4 parallel jobs
using the following command:

  make -j4 X310_IP

Or, build two X310 bitstreams simultaneously:

  make -j2 X310_XG X310_HG


Original-commit: 4b03e237a96ee277eefff257d65b08708c38662c
This commit is contained in:
Wade Fife
2022-08-16 10:16:22 -05:00
parent 50bf9c3ae5
commit 81bb2ae28f
100 changed files with 608 additions and 224 deletions
Download Patch File Download Diff File Expand all files Collapse all files
top/x300/ip/aurora_64b66b_pcs_pma/Makefile.inc
+6 -2
View File
@@ -28,7 +28,11 @@ IP_AURORA_64B66B_PCS_PMA_SRCS = $(IP_BUILD_DIR)/aurora_64b66b_pcs_pma/aurora_64b
IP_AURORA_64B66B_PCS_PMA_OUTS = $(addprefix $(IP_BUILD_DIR)/aurora_64b66b_pcs_pma/, \
aurora_64b66b_pcs_pma.xci.out \
)
)
$(IP_AURORA_64B66B_PCS_PMA_SRCS) $(IP_AURORA_64B66B_PCS_PMA_OUTS) $(IP_AURORA_64B66B_PCS_PMA_EXAMPLE_SRCS): $(IP_DIR)/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.xci
.INTERMEDIATE: IP_AURORA_64B66B_PCS_PMA_TRGT
$(IP_AURORA_64B66B_PCS_PMA_SRCS) $(IP_AURORA_64B66B_PCS_PMA_OUTS) $(IP_AURORA_64B66B_PCS_PMA_EXAMPLE_SRCS): IP_AURORA_64B66B_PCS_PMA_TRGT
@:
IP_AURORA_64B66B_PCS_PMA_TRGT: $(IP_DIR)/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.xci
$(call BUILD_VIVADO_IP,aurora_64b66b_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),1)
top/x300/ip/axi4_dualport_sram/Makefile.inc
+6 -2
View File
@@ -9,7 +9,11 @@ IP_AXI4_BRAM_SRCS = $(IP_BUILD_DIR)/axi4_dualport_sram/axi4_dualport_sram.xci
IP_AXI4_BRAM_OUTS = $(addprefix $(IP_BUILD_DIR)/axi4_dualport_sram/, \
axi4_dualport_sram.xci.out \
synth/axi4_dualport_sram.vhd \
)
)
$(IP_AXI4_BRAM_SRCS) $(IP_AXI4_BRAM_OUTS) : $(IP_DIR)/axi4_dualport_sram/axi4_dualport_sram.xci
.INTERMEDIATE: IP_AXI4_BRAM_TRGT
$(IP_AXI4_BRAM_SRCS) $(IP_AXI4_BRAM_OUTS): IP_AXI4_BRAM_TRGT
@:
IP_AXI4_BRAM_TRGT: $(IP_DIR)/axi4_dualport_sram/axi4_dualport_sram.xci
$(call BUILD_VIVADO_IP,axi4_dualport_sram,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0)
top/x300/ip/axi64_4k_2clk_fifo/Makefile.inc
+6 -2
View File
@@ -9,7 +9,11 @@ IP_AXI64_4K_2CLK_FIFO_SRCS = $(IP_BUILD_DIR)/axi64_4k_2clk_fifo/axi64_4k_2clk_fi
IP_AXI64_4K_2CLK_FIFO_OUTS = $(addprefix $(IP_BUILD_DIR)/axi64_4k_2clk_fifo/, \
axi64_4k_2clk_fifo.xci.out \
synth/axi64_4k_2clk_fifo.vhd \
)
)
$(IP_AXI64_4K_2CLK_FIFO_SRCS) $(IP_AXI64_4K_2CLK_FIFO_OUTS) : $(IP_DIR)/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci
.INTERMEDIATE: IP_AXI64_4K_2CLK_FIFO_TRGT
$(IP_AXI64_4K_2CLK_FIFO_SRCS) $(IP_AXI64_4K_2CLK_FIFO_OUTS): IP_AXI64_4K_2CLK_FIFO_TRGT
@:
IP_AXI64_4K_2CLK_FIFO_TRGT: $(IP_DIR)/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci
$(call BUILD_VIVADO_IP,axi64_4k_2clk_fifo,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0)
top/x300/ip/axi64_8k_2clk_fifo/Makefile.inc
+6 -2
View File
@@ -9,7 +9,11 @@ IP_AXI64_8K_2CLK_FIFO_SRCS = $(IP_BUILD_DIR)/axi64_8k_2clk_fifo/axi64_8k_2clk_fi
IP_AXI64_8K_2CLK_FIFO_OUTS = $(addprefix $(IP_BUILD_DIR)/axi64_8k_2clk_fifo/, \
axi64_8k_2clk_fifo.xci.out \
synth/axi64_8k_2clk_fifo.vhd \
)
)
$(IP_AXI64_8K_2CLK_FIFO_SRCS) $(IP_AXI64_8K_2CLK_FIFO_OUTS) : $(IP_DIR)/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci
.INTERMEDIATE: IP_AXI64_8K_2CLK_FIFO_TRGT
$(IP_AXI64_8K_2CLK_FIFO_SRCS) $(IP_AXI64_8K_2CLK_FIFO_OUTS): IP_AXI64_8K_2CLK_FIFO_TRGT
@:
IP_AXI64_8K_2CLK_FIFO_TRGT: $(IP_DIR)/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci
$(call BUILD_VIVADO_IP,axi64_8k_2clk_fifo,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0)
top/x300/ip/axi_intercon_2x64_128_bd/Makefile.inc
+5 -1
View File
@@ -13,7 +13,11 @@ axi_intercon_2x64_128_bd.bd.out \
axi_intercon_2x64_128_bd_ooc.xdc \
)
.INTERMEDIATE: IP_AXI_INTERCON_2X64_128_BD_TRGT
$(IP_AXI_INTERCON_2X64_128_BD_SRCS) $(IP_AXI_INTERCON_2X64_128_BD_OUTS): IP_AXI_INTERCON_2X64_128_BD_TRGT
@:
# The cp below is a workaround for a Vivado issue where it is pulling in wrong sources
$(IP_AXI_INTERCON_2X64_128_BD_SRCS) $(IP_AXI_INTERCON_2X64_128_BD_OUTS) : $(IP_DIR)/axi_intercon_2x64_128_bd/axi_intercon_2x64_128_bd.bd
IP_AXI_INTERCON_2X64_128_BD_TRGT: $(IP_DIR)/axi_intercon_2x64_128_bd/axi_intercon_2x64_128_bd.bd
$(call BUILD_VIVADO_BD,axi_intercon_2x64_128_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR))
cp -f $(IP_BUILD_DIR)/axi_intercon_2x64_128_bd/synth/axi_intercon_2x64_128_bd.v $(IP_BUILD_DIR)/axi_intercon_2x64_128_bd/hdl/axi_intercon_2x64_128_bd.v
top/x300/ip/bootram/Makefile.inc
+6 -2
View File
@@ -9,7 +9,11 @@ IP_BOOTRAM_SRCS = $(IP_BUILD_DIR)/bootram/bootram.xci
IP_BOOTRAM_OUTS = $(addprefix $(IP_BUILD_DIR)/bootram/, \
bootram.xci.out \
synth/bootram.vhd \
)
)
$(IP_BOOTRAM_SRCS) $(IP_BOOTRAM_OUTS) : $(IP_DIR)/bootram/bootram.xci $(IP_DIR)/bootram/bootram.coe
.INTERMEDIATE: IP_BOOTRAM_TRGT
$(IP_BOOTRAM_SRCS) $(IP_BOOTRAM_OUTS): IP_BOOTRAM_TRGT
@:
IP_BOOTRAM_TRGT: $(IP_DIR)/bootram/bootram.xci $(IP_DIR)/bootram/bootram.coe
$(call BUILD_VIVADO_IP,bootram,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0)
top/x300/ip/bus_clk_gen/Makefile.inc
+6 -2
View File
@@ -9,7 +9,11 @@ IP_BUS_CLK_GEN_SRCS = $(IP_BUILD_DIR)/bus_clk_gen/bus_clk_gen.xci
IP_BUS_CLK_GEN_OUTS = $(addprefix $(IP_BUILD_DIR)/bus_clk_gen/, \
bus_clk_gen.xci.out \
bus_clk_gen.v \
)
)
$(IP_BUS_CLK_GEN_SRCS) $(IP_BUS_CLK_GEN_OUTS) : $(IP_DIR)/bus_clk_gen/bus_clk_gen.xci
.INTERMEDIATE: IP_BUS_CLK_GEN_TRGT
$(IP_BUS_CLK_GEN_SRCS) $(IP_BUS_CLK_GEN_OUTS): IP_BUS_CLK_GEN_TRGT
@:
IP_BUS_CLK_GEN_TRGT: $(IP_DIR)/bus_clk_gen/bus_clk_gen.xci
$(call BUILD_VIVADO_IP,bus_clk_gen,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0)
top/x300/ip/ddr3_32bit/Makefile.inc
+4 -1
View File
@@ -19,8 +19,11 @@ ddr3_32bit/example_design/sim/ddr3_model.sv \
ddr3_32bit/example_design/sim/ddr3_model_parameters.vh \
)
.INTERMEDIATE: IP_DDR3_32BIT_TRGT
$(IP_DDR3_32BIT_SRCS) $(IP_DDR3_32BIT_OUTS): IP_DDR3_32BIT_TRGT
@:
$(IP_DDR3_32BIT_SRCS) $(IP_DDR3_32BIT_OUTS) : $(IP_DIR)/ddr3_32bit/ddr3_32bit.xci $(IP_DIR)/ddr3_32bit/mig_*.prj
IP_DDR3_32BIT_TRGT: $(IP_DIR)/ddr3_32bit/ddr3_32bit.xci $(IP_DIR)/ddr3_32bit/mig_*.prj
cp -f $(IP_DIR)/ddr3_32bit/mig_$(subst /,,$(PART_ID)).prj $(IP_DIR)/ddr3_32bit/mig_a.prj # Note: This won't allow parallel IP builds
$(call BUILD_VIVADO_IP,ddr3_32bit,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0)
rm -f $(IP_DIR)/ddr3_32bit/mig_a.prj
top/x300/ip/fifo_4k_2clk/Makefile.inc
+6 -2
View File
@@ -9,7 +9,11 @@ IP_FIFO_4K_2CLK_SRCS = $(IP_BUILD_DIR)/fifo_4k_2clk/fifo_4k_2clk.xci
IP_FIFO_4K_2CLK_OUTS = $(addprefix $(IP_BUILD_DIR)/fifo_4k_2clk/, \
fifo_4k_2clk.xci.out \
synth/fifo_4k_2clk.vhd \
)
)
$(IP_FIFO_4K_2CLK_SRCS) $(IP_FIFO_4K_2CLK_OUTS) : $(IP_DIR)/fifo_4k_2clk/fifo_4k_2clk.xci
.INTERMEDIATE: IP_FIFO_4K_2CLK_TRGT
$(IP_FIFO_4K_2CLK_SRCS) $(IP_FIFO_4K_2CLK_OUTS): IP_FIFO_4K_2CLK_TRGT
@:
IP_FIFO_4K_2CLK_TRGT: $(IP_DIR)/fifo_4k_2clk/fifo_4k_2clk.xci
$(call BUILD_VIVADO_IP,fifo_4k_2clk,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0)
top/x300/ip/fifo_short_2clk/Makefile.inc
+6 -2
View File
@@ -9,7 +9,11 @@ IP_FIFO_SHORT_2CLK_SRCS = $(IP_BUILD_DIR)/fifo_short_2clk/fifo_short_2clk.xci
IP_FIFO_SHORT_2CLK_OUTS = $(addprefix $(IP_BUILD_DIR)/fifo_short_2clk/, \
fifo_short_2clk.xci.out \
synth/fifo_short_2clk.vhd \
)
)
$(IP_FIFO_SHORT_2CLK_SRCS) $(IP_FIFO_SHORT_2CLK_OUTS) : $(IP_DIR)/fifo_short_2clk/fifo_short_2clk.xci
.INTERMEDIATE: IP_FIFO_SHORT_2CLK_TRGT
$(IP_FIFO_SHORT_2CLK_SRCS) $(IP_FIFO_SHORT_2CLK_OUTS): IP_FIFO_SHORT_2CLK_TRGT
@:
IP_FIFO_SHORT_2CLK_TRGT: $(IP_DIR)/fifo_short_2clk/fifo_short_2clk.xci
$(call BUILD_VIVADO_IP,fifo_short_2clk,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0)
top/x300/ip/input_sample_fifo/Makefile.inc
+6 -2
View File
@@ -9,7 +9,11 @@ IP_INPUT_SAMPLE_FIFO_SRCS = $(IP_BUILD_DIR)/input_sample_fifo/input_sample_fifo.
IP_INPUT_SAMPLE_FIFO_OUTS = $(addprefix $(IP_BUILD_DIR)/input_sample_fifo/, \
nput_sample_fifo.xci.out \
synth/input_sample_fifo.vhd \
)
)
$(IP_INPUT_SAMPLE_FIFO_SRCS) $(IP_INPUT_SAMPLE_FIFO_OUTS) : $(IP_DIR)/input_sample_fifo/input_sample_fifo.xci
.INTERMEDIATE: IP_INPUT_SAMPLE_FIFO_TRGT
$(IP_INPUT_SAMPLE_FIFO_SRCS) $(IP_INPUT_SAMPLE_FIFO_OUTS): IP_INPUT_SAMPLE_FIFO_TRGT
@:
IP_INPUT_SAMPLE_FIFO_TRGT: $(IP_DIR)/input_sample_fifo/input_sample_fifo.xci
$(call BUILD_VIVADO_IP,input_sample_fifo,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0)
top/x300/ip/one_gig_eth_pcs_pma/Makefile.inc
+5 -1
View File
@@ -42,7 +42,11 @@ synth/transceiver/one_gig_eth_pcs_pma_rx_startup_fsm.v \
$(IP_ONE_GIG_ETH_PCS_PMA_EXAMPLE_SRCS) : $(IP_ONE_GIG_ETH_PCS_PMA_OUTS)
$(IP_ONE_GIG_ETH_PCS_PMA_SRCS) $(IP_ONE_GIG_ETH_PCS_PMA_OUTS) : $(IP_DIR)/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci
.INTERMEDIATE: IP_ONE_GIG_ETH_PCS_PMA_TRGT
$(IP_ONE_GIG_ETH_PCS_PMA_SRCS) $(IP_ONE_GIG_ETH_PCS_PMA_OUTS): IP_ONE_GIG_ETH_PCS_PMA_TRGT
@:
IP_ONE_GIG_ETH_PCS_PMA_TRGT: $(IP_DIR)/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci
$(call BUILD_VIVADO_IP,one_gig_eth_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),1)
cp $(IP_BUILD_DIR)/one_gig_eth_pcs_pma_ex/imports/one_gig_eth_pcs_pma_clocking.v $(IP_BUILD_DIR)/one_gig_eth_pcs_pma_ex/imports/one_gig_eth_pcs_pma_clocking.v.orig
patch $(IP_BUILD_DIR)/one_gig_eth_pcs_pma_ex/imports/one_gig_eth_pcs_pma_clocking.v $(IP_DIR)/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma_clocking.v.patch
top/x300/ip/pcie_clk_gen/Makefile.inc
+6 -2
View File
@@ -9,7 +9,11 @@ IP_PCIE_CLK_GEN_SRCS = $(IP_BUILD_DIR)/pcie_clk_gen/pcie_clk_gen.xci
IP_PCIE_CLK_GEN_OUTS = $(addprefix $(IP_BUILD_DIR)/pcie_clk_gen/, \
pcie_clk_gen.xci.out \
pcie_clk_gen.v \
)
)
$(IP_PCIE_CLK_GEN_SRCS) $(IP_PCIE_CLK_GEN_OUTS) : $(IP_DIR)/pcie_clk_gen/pcie_clk_gen.xci
.INTERMEDIATE: IP_PCIE_CLK_GEN_TRGT
$(IP_PCIE_CLK_GEN_SRCS) $(IP_PCIE_CLK_GEN_OUTS): IP_PCIE_CLK_GEN_TRGT
@:
IP_PCIE_CLK_GEN_TRGT: $(IP_DIR)/pcie_clk_gen/pcie_clk_gen.xci
$(call BUILD_VIVADO_IP,pcie_clk_gen,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0)
top/x300/ip/radio_clk_gen/Makefile.inc
+7 -3
View File
@@ -9,11 +9,15 @@ IP_RADIO_CLK_GEN_SRCS = $(IP_BUILD_DIR)/radio_clk_gen/radio_clk_gen.xci
IP_RADIO_CLK_GEN_OUTS = $(addprefix $(IP_BUILD_DIR)/radio_clk_gen/, \
radio_clk_gen.xci.out \
radio_clk_gen.v \
)
)
# We have to patch the XDC file to remove constraints on the source clock for the module
# All timing constraints are handled in one place (timing.xdc)
$(IP_RADIO_CLK_GEN_SRCS) $(IP_RADIO_CLK_GEN_OUTS) : $(IP_DIR)/radio_clk_gen/radio_clk_gen.xci
.INTERMEDIATE: IP_RADIO_CLK_GEN_TRGT
$(IP_RADIO_CLK_GEN_SRCS) $(IP_RADIO_CLK_GEN_OUTS): IP_RADIO_CLK_GEN_TRGT
@:
IP_RADIO_CLK_GEN_TRGT: $(IP_DIR)/radio_clk_gen/radio_clk_gen.xci
$(call BUILD_VIVADO_IP,radio_clk_gen,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0)
patch $(IP_BUILD_DIR)/radio_clk_gen/radio_clk_gen.xdc $(IP_DIR)/radio_clk_gen/radio_clk_gen.xdc.patch
top/x300/ip/ten_gig_eth_pcs_pma/Makefile.inc
+7 -4
View File
@@ -15,7 +15,7 @@ ten_gig_eth_pcs_pma_ff_synchronizer_rst2.v \
ten_gig_eth_pcs_pma_gt_common.v \
ten_gig_eth_pcs_pma_shared_clock_and_reset.v \
ten_gig_eth_pcs_pma_support.v \
)
)
IP_TEN_GIG_ETH_PCS_PMA_SRCS = $(IP_BUILD_DIR)/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci
@@ -33,10 +33,13 @@ synth/ten_gig_eth_pcs_pma_ff_synchronizer.v \
synth/ten_gig_eth_pcs_pma.v \
synth/ten_gig_eth_pcs_pma_gtwizard_10gbaser_gt.v \
synth/ten_gig_eth_pcs_pma.xdc \
)
)
$(IP_TEN_GIG_ETH_PCS_PMA_EXAMPLE_SRCS) : $(IP_TEN_GIG_ETH_PCS_PMA_OUTS)
$(IP_TEN_GIG_ETH_PCS_PMA_SRCS) $(IP_TEN_GIG_ETH_PCS_PMA_OUTS) : $(IP_DIR)/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci
$(call BUILD_VIVADO_IP,ten_gig_eth_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),1)
.INTERMEDIATE: IP_TEN_GIG_ETH_PCS_PMA_TRGT
$(IP_TEN_GIG_ETH_PCS_PMA_SRCS) $(IP_TEN_GIG_ETH_PCS_PMA_OUTS): IP_TEN_GIG_ETH_PCS_PMA_TRGT
@:
IP_TEN_GIG_ETH_PCS_PMA_TRGT: $(IP_DIR)/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci
$(call BUILD_VIVADO_IP,ten_gig_eth_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),1)