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fpga: Update makefiles to allow parallel FPGA builds

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This adds the ability to do IP generation and FPGA builds using the
--jobs (-j) option with Make. For example, rather than generating each
IP one after another, you can generate up to N at a time using N Vivado
instances. This greatly reduces the IP generation time. Similarly,
parallel jobs can be used to easily build different FPGA variants
simultaneously.

Because FPGA builds can consume a lot of memory, care must be taken to
ensure that the number of jobs is not too high for the amount of memory
available.

New IP make targets were added for each USRP so that IP can be built
separately from the FPGA. The IP targets are now a dependency on each
FPGA target.

For example, you can generate the IP for X310 using 4 parallel jobs
using the following command:

  make -j4 X310_IP

Or, build two X310 bitstreams simultaneously:

  make -j2 X310_XG X310_HG


Original-commit: 4b03e237a96ee277eefff257d65b08708c38662c
This commit is contained in:
Wade Fife
2022-08-16 10:16:22 -05:00
parent 50bf9c3ae5
commit 81bb2ae28f
100 changed files with 608 additions and 224 deletions
Download Patch File Download Diff File Expand all files Collapse all files
top/n3xx/Makefile
+29 -18
View File
@@ -58,6 +58,7 @@ TOP ?= n3xx
# Definitions: See above (*_DEFS)
# Defaults: See above (*_DEFAULTS)
vivado_build = make -f Makefile.n3xx.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" $3
vivado_ip = make -f Makefile.n3xx.inc viv_ip NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" $3
# post_build($1=Device, $2=Option)
ifeq ($(TARGET),bin)
@@ -78,93 +79,103 @@ endif
all: N300_HG N300_XG N310_HG N310_XG N320_HG N320_XG ##(Default target)
##N300_IP: Build IP for N300 only.
N300_IP:
+$(call vivado_ip,N300,$(HG_DEFS) N300=1,$(N300_DEFAULTS))
##N310_IP: Build IP for N310/N320.
##N320_IP: Build IP for N310/N320.
N310_IP N320_IP: N3X0_IP
N3X0_IP:
+$(call vivado_ip,N310,$(HG_DEFS) N310=1,$(N310_DEFAULTS))
##N310_WX: 1GigE White Rabbit on SFP+ Port0, 10Gig on SFP+ Port1.
N310_WX: build/usrp_n310_fpga_WX.dts
N310_WX: N3X0_IP build/usrp_n310_fpga_WX.dts
$(call vivado_build,N310,$(WX_DEFS) N310=1,$(N310_DEFAULTS))
$(call post_build,N310,WX)
##N310_HG: 1GigE on SFP+ Port0, 10Gig on SFP+ Port1.
N310_HG: build/usrp_n310_fpga_HG.dts
N310_HG: N3X0_IP build/usrp_n310_fpga_HG.dts
$(call vivado_build,N310,$(HG_DEFS) N310=1,$(N310_DEFAULTS))
$(call post_build,N310,HG)
##N310_XG: 10GigE on SFP+ Port0, 10Gig on SFP+ Port1.
N310_XG: build/usrp_n310_fpga_XG.dts
N310_XG: N3X0_IP build/usrp_n310_fpga_XG.dts
$(call vivado_build,N310,$(XG_DEFS) N310=1,$(N310_DEFAULTS))
$(call post_build,N310,XG)
##N310_HA: 1Gig on SFP+ Port0, Aurora on SFP+ Port1.
N310_HA: build/usrp_n310_fpga_HA.dts
N310_HA: N3X0_IP build/usrp_n310_fpga_HA.dts
$(call vivado_build,N310,$(HA_DEFS) N310=1,$(N310_DEFAULTS))
$(call post_build,N310,HA)
##N310_XA: 10Gig on SFP+ Port0, Aurora on SFP+ Port1.
N310_XA: build/usrp_n310_fpga_XA.dts
N310_XA: N3X0_IP build/usrp_n310_fpga_XA.dts
$(call vivado_build,N310,$(XA_DEFS) N310=1,$(N310_DEFAULTS))
$(call post_build,N310,XA)
##N310_AA: Aurora on SFP+ Port0, Aurora on SFP+ Port1.
N310_AA: build/usrp_n310_fpga_AA.dts
N310_AA: N3X0_IP build/usrp_n310_fpga_AA.dts
$(call vivado_build,N310,$(AA_DEFS) N310=1,$(N310AA_DEFAULTS))
$(call post_build,N310,AA)
##N300_WX: 1GigE White Rabbit on SFP+ Port0, 10Gig on SFP+ Port1.
N300_WX: build/usrp_n300_fpga_WX.dts
N300_WX: N300_IP build/usrp_n300_fpga_WX.dts
$(call vivado_build,N300,$(WX_DEFS) N300=1,$(N300_DEFAULTS))
$(call post_build,N300,WX)
##N300_HG: 1GigE on SFP+ Port0, 10Gig on SFP+ Port1.
N300_HG: build/usrp_n300_fpga_HG.dts
N300_HG: N300_IP build/usrp_n300_fpga_HG.dts
$(call vivado_build,N300,$(HG_DEFS) N300=1,$(N300_DEFAULTS))
$(call post_build,N300,HG)
##N300_XG: 10GigE on SFP+ Port0, 10Gig on SFP+ Port1.
N300_XG: build/usrp_n300_fpga_XG.dts
N300_XG: N300_IP build/usrp_n300_fpga_XG.dts
$(call vivado_build,N300,$(XG_DEFS) N300=1,$(N300_DEFAULTS))
$(call post_build,N300,XG)
##N300_HA: 1Gig on SFP+ Port0, Aurora on SFP+ Port1.
N300_HA: build/usrp_n300_fpga_HA.dts
N300_HA: N300_IP build/usrp_n300_fpga_HA.dts
$(call vivado_build,N300,$(HA_DEFS) N300=1,$(N300_DEFAULTS))
$(call post_build,N300,HA)
##N300_XA: 10Gig on SFP+ Port0, Aurora on SFP+ Port1.
N300_XA: build/usrp_n300_fpga_XA.dts
N300_XA: N300_IP build/usrp_n300_fpga_XA.dts
$(call vivado_build,N300,$(XA_DEFS) N300=1,$(N300_DEFAULTS))
$(call post_build,N300,XA)
##N300_AA: Aurora on SFP+ Port0, Aurora on SFP+ Port1.
N300_AA: build/usrp_n300_fpga_AA.dts
N300_AA: N300_IP build/usrp_n300_fpga_AA.dts
$(call vivado_build,N300,$(AA_DEFS) N300=1,$(N300AA_DEFAULTS))
$(call post_build,N300,AA)
##N320_WX: 1GigE White Rabbit on SFP+ Port0, 10Gig on SFP+ Port1.
N320_WX: build/usrp_n320_fpga_WX.dts
N320_WX: N3X0_IP build/usrp_n320_fpga_WX.dts
$(call vivado_build,N320,$(WX_DEFS) N320=1,$(N320_DEFAULTS))
$(call post_build,N320,WX)
##N320_HG: 1GigE on SFP+ Port0, 10Gig on SFP+ Port1.
N320_HG: build/usrp_n320_fpga_HG.dts
N320_HG: N3X0_IP build/usrp_n320_fpga_HG.dts
$(call vivado_build,N320,$(HG_DEFS) N320=1,$(N320_DEFAULTS))
$(call post_build,N320,HG)
##N320_XG: 10GigE on SFP+ Port0, 10Gig on SFP+ Port1.
N320_XG: build/usrp_n320_fpga_XG.dts
N320_XG: N3X0_IP build/usrp_n320_fpga_XG.dts
$(call vivado_build,N320,$(XG_DEFS) N320=1,$(N320_DEFAULTS))
$(call post_build,N320,XG)
##N320_XQ: WR on SFP+ Port0, 10Gig on QSFP+ Port0,1.
N320_XQ: build/usrp_n320_fpga_XQ.dts
N320_XQ: N3X0_IP build/usrp_n320_fpga_XQ.dts
$(call vivado_build,N320,$(XQ_DEFS) N320=1,$(N320_DEFAULTS))
$(call post_build,N320,XQ)
##N320_AQ: 10Gig on SFP+ Port0,1 Aurora on QSFP+ Port0,1,2,3.
N320_AQ: build/usrp_n320_fpga_AQ.dts
N320_AQ: N3X0_IP build/usrp_n320_fpga_AQ.dts
$(call vivado_build,N320,$(AQ_DEFS) N320=1,$(N320_DEFAULTS))
$(call post_build,N320,AQ)
##N320_AA: Aurora on SFP+ Port0, Aurora on SFP+ Port1.
N320_AA: build/usrp_n320_fpga_AA.dts
N320_AA: N3X0_IP build/usrp_n320_fpga_AA.dts
$(call vivado_build,N320,$(AA_DEFS) N320=1,$(N320AA_DEFAULTS))
$(call post_build,N320,AA)