fpga: x400: cpld: Add support for X410 motherboard CPLD
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Original-commit: 7015f5ed2d495f3908773b7c7d74864d0cc3871a
This commit is contained in:
Max Köhler
committed by
Aaron Rossetto
Aaron Rossetto
co-authored by
Humberto Jimenez
Javier Valenzuela
Humberto Jimenez
Javier Valenzuela
parent
61782b02d7
commit
7e59e9516d
@@ -0,0 +1,3 @@
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# generate files
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clkctrl/
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clkctrl.sopcinfo
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@@ -0,0 +1,73 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<system name="$${FILENAME}">
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<component
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name="$${FILENAME}"
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displayName="$${FILENAME}"
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version="1.0"
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description=""
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tags="INTERNAL_COMPONENT=true"
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categories="" />
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<parameter name="bonusData"><![CDATA[bonusData
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{
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element altclkctrl_0
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{
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datum _sortIndex
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{
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value = "0";
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type = "int";
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}
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}
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}
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]]></parameter>
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<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
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<parameter name="device" value="10M04SAU169I7G" />
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<parameter name="deviceFamily" value="MAX 10" />
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<parameter name="deviceSpeedGrade" value="7" />
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<parameter name="fabricMode" value="QSYS" />
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<parameter name="generateLegacySim" value="false" />
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<parameter name="generationId" value="0" />
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<parameter name="globalResetBus" value="false" />
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<parameter name="hdlLanguage" value="VERILOG" />
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<parameter name="hideFromIPCatalog" value="true" />
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<parameter name="lockedInterfaceDefinition" value="" />
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<parameter name="maxAdditionalLatency" value="1" />
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<parameter name="projectName" value="" />
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<parameter name="sopcBorderPoints" value="false" />
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<parameter name="systemHash" value="0" />
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<parameter name="testBenchDutName" value="" />
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<parameter name="timeStamp" value="0" />
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<parameter name="useTestBenchNamingPattern" value="false" />
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<instanceScript></instanceScript>
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<interface
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name="altclkctrl_input"
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internal="altclkctrl_0.altclkctrl_input"
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type="conduit"
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dir="end">
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<port name="inclk" internal="inclk" />
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<port name="ena" internal="ena" />
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</interface>
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<interface
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name="altclkctrl_output"
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internal="altclkctrl_0.altclkctrl_output"
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type="conduit"
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dir="end">
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<port name="outclk" internal="outclk" />
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</interface>
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<module
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name="altclkctrl_0"
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kind="altclkctrl"
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version="18.1"
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enabled="1"
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autoexport="1">
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<parameter name="CLOCK_TYPE" value="1" />
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<parameter name="DEVICE_FAMILY" value="MAX 10" />
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<parameter name="ENA_REGISTER_MODE" value="1" />
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<parameter name="GUI_USE_ENA" value="true" />
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<parameter name="NUMBER_OF_CLOCKS" value="1" />
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<parameter name="USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION" value="false" />
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</module>
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<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
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<interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
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<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
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<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
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</system>
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@@ -0,0 +1,2 @@
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# GUI logfile
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PcieCmi.qarlog
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Binary file not shown.
@@ -0,0 +1,38 @@
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--
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-- Copyright 2021 Ettus Research, a National Instruments Brand
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--
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-- SPDX-License-Identifier: LGPL-3.0-or-later
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--
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-- Module: PcieCmi
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--
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-- Description:
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--
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-- This is an automatically generated file.
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-- Do not modify this file directly!
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity PcieCmi is
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generic (
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kSimulation : natural := 0
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);
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port (
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Clk : in std_logic ;
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acReset : in std_logic ;
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cSerialNumber : in std_logic_vector (39 downto 0);
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cBoardIsReady : in std_logic ;
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cCmiReset : out std_logic ;
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cOtherSideDetected : out std_logic ;
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aCblPrsnt_n : in std_logic ;
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aSdaIn : in std_logic ;
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aSdaOut : out std_logic ;
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aSclIn : in std_logic ;
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aSclOut : out std_logic
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);
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end entity PcieCmi;
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architecture rtl of PcieCmi is
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begin
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end architecture rtl;
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@@ -0,0 +1,93 @@
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--
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-- Copyright 2021 Ettus Research, a National Instruments Brand
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--
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-- SPDX-License-Identifier: LGPL-3.0-or-later
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--
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-- Module: PcieCmiWrapper
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--
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-- Description:
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--
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-- This is an automatically generated file.
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-- Do not modify this file directly!
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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--synopsys translate_off
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--For synthesis, netlist comes from an qxp and there is no external library
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--For simulation in client, netlist comes from PcieCmiLib external library
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--For simulation in dev branch, netlist comes from work library.
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--Binding will work fine in both simulation cases as long as PcieCmi is compiled
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-- to either library. In dev branch PcieCmiLib will be an empty library just so
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-- ModelSim doesn't complain.
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library PcieCmiLib;
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--synopsys translate_on
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entity PcieCmiWrapper is
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generic (
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kSimulation : natural := 0 -- set to 1 to speedup simulation
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);
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port (
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Clk : in std_logic; -- 40 MHz clock
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acReset : in std_logic;
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cSerialNumber : in std_logic_vector(39 downto 0);
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cBoardIsReady : in std_logic;
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cCmiReset : out std_logic;
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cOtherSideDetected : out std_logic;
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aCblPrsnt_n : in std_logic;
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aSdaIn : in std_logic;
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aSdaOut : out std_logic;
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aSclIn : in std_logic;
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aSclOut : out std_logic
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);
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end PcieCmiWrapper;
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architecture rtl of PcieCmiWrapper is
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component PcieCmi
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generic (kSimulation : natural := 0);
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port (
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Clk : in std_logic;
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acReset : in std_logic;
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cSerialNumber : in std_logic_vector(39 downto 0);
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cBoardIsReady : in std_logic;
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cCmiReset : out std_logic;
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cOtherSideDetected : out std_logic;
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aCblPrsnt_n : in std_logic;
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aSdaIn : in std_logic;
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aSdaOut : out std_logic;
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aSclIn : in std_logic;
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aSclOut : out std_logic);
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end component;
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begin
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-- Just forward all signals to lower level entity.
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-- Leave the simulation generic in place as it important to be able to
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-- simulate the netlist in reasonable time. For the synthesis in the client
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-- the generic is ignored as the netlist is translated with kSimulation set to
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-- default value and "overwrites" it.
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--vhook PcieCmi
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PcieCmix: PcieCmi
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generic map (kSimulation => kSimulation) --natural:=0
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port map (
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Clk => Clk, --in std_logic
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acReset => acReset, --in std_logic
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cSerialNumber => cSerialNumber, --in std_logic_vector(39:0)
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cBoardIsReady => cBoardIsReady, --in std_logic
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cCmiReset => cCmiReset, --out std_logic
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cOtherSideDetected => cOtherSideDetected, --out std_logic
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aCblPrsnt_n => aCblPrsnt_n, --in std_logic
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aSdaIn => aSdaIn, --in std_logic
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aSdaOut => aSdaOut, --out std_logic
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aSclIn => aSclIn, --in std_logic
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aSclOut => aSclOut); --out std_logic
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end architecture rtl;
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@@ -0,0 +1,3 @@
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# generate files
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on_chip_flash/
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on_chip_flash.sopcinfo
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@@ -0,0 +1,90 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<system name="$${FILENAME}">
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<component
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name="$${FILENAME}"
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displayName="$${FILENAME}"
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version="1.0"
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description=""
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tags="INTERNAL_COMPONENT=true"
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categories="System" />
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<parameter name="bonusData"><![CDATA[bonusData
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{
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element onchip_flash_0
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{
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datum _sortIndex
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{
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value = "0";
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type = "int";
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}
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}
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}
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]]></parameter>
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<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
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<parameter name="device" value="10M04SAU169I7G" />
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<parameter name="deviceFamily" value="MAX 10" />
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<parameter name="deviceSpeedGrade" value="7" />
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<parameter name="fabricMode" value="QSYS" />
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<parameter name="generateLegacySim" value="false" />
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<parameter name="generationId" value="0" />
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<parameter name="globalResetBus" value="false" />
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<parameter name="hdlLanguage" value="VERILOG" />
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<parameter name="hideFromIPCatalog" value="true" />
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<parameter name="lockedInterfaceDefinition" value="" />
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<parameter name="maxAdditionalLatency" value="1" />
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<parameter name="projectName" value="" />
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<parameter name="sopcBorderPoints" value="false" />
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<parameter name="systemHash" value="0" />
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<parameter name="testBenchDutName" value="" />
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<parameter name="timeStamp" value="0" />
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<parameter name="useTestBenchNamingPattern" value="false" />
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<instanceScript></instanceScript>
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<interface name="clk" internal="onchip_flash_0.clk" type="clock" dir="end">
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<port name="clock" internal="clock" />
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</interface>
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<interface name="csr" internal="onchip_flash_0.csr" type="avalon" dir="end">
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<port name="avmm_csr_addr" internal="avmm_csr_addr" />
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<port name="avmm_csr_read" internal="avmm_csr_read" />
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<port name="avmm_csr_writedata" internal="avmm_csr_writedata" />
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<port name="avmm_csr_write" internal="avmm_csr_write" />
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<port name="avmm_csr_readdata" internal="avmm_csr_readdata" />
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</interface>
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<interface name="data" internal="onchip_flash_0.data" type="avalon" dir="end">
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<port name="avmm_data_addr" internal="avmm_data_addr" />
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<port name="avmm_data_read" internal="avmm_data_read" />
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<port name="avmm_data_writedata" internal="avmm_data_writedata" />
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<port name="avmm_data_write" internal="avmm_data_write" />
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<port name="avmm_data_readdata" internal="avmm_data_readdata" />
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<port name="avmm_data_waitrequest" internal="avmm_data_waitrequest" />
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<port name="avmm_data_readdatavalid" internal="avmm_data_readdatavalid" />
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<port name="avmm_data_burstcount" internal="avmm_data_burstcount" />
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</interface>
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<interface name="nreset" internal="onchip_flash_0.nreset" type="reset" dir="end">
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<port name="reset_n" internal="reset_n" />
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</interface>
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<module
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name="onchip_flash_0"
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kind="altera_onchip_flash"
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version="18.1"
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enabled="1"
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autoexport="1">
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<parameter name="AUTO_CLOCK_RATE" value="0" />
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<parameter name="CLOCK_FREQUENCY" value="50.0" />
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<parameter name="CONFIGURATION_MODE">Single Compressed Image</parameter>
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<parameter name="CONFIGURATION_SCHEME">Internal Configuration</parameter>
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<parameter name="DATA_INTERFACE" value="Parallel" />
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<parameter name="DEVICE_FAMILY" value="MAX 10" />
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<parameter name="PART_NAME" value="10M04SAU169I7G" />
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<parameter name="READ_BURST_COUNT" value="8" />
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<parameter name="READ_BURST_MODE" value="Incrementing" />
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<parameter name="SECTOR_ACCESS_MODE">Read and write,Read and write,Read and write,Read and write,Read and write</parameter>
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<parameter name="autoInitializationFileName">$${FILENAME}_onchip_flash_0</parameter>
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<parameter name="initFlashContent" value="false" />
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<parameter name="initializationFileName">altera_onchip_flash.hex</parameter>
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<parameter name="initializationFileNameForSim">altera_onchip_flash.dat</parameter>
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<parameter name="useNonDefaultInitFile" value="false" />
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</module>
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<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
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<interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
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<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
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<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
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</system>
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@@ -0,0 +1,74 @@
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set_global_assignment -entity "oddr" -library "oddr" -name IP_TOOL_NAME "altera_gpio_lite"
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set_global_assignment -entity "oddr" -library "oddr" -name IP_TOOL_VERSION "20.1"
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set_global_assignment -entity "oddr" -library "oddr" -name IP_TOOL_ENV "mwpim"
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set_global_assignment -library "oddr" -name MISC_FILE [file join $::quartus(qip_path) "oddr.cmp"]
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set_global_assignment -entity "oddr" -library "oddr" -name IP_TARGETED_DEVICE_FAMILY "MAX 10"
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set_global_assignment -entity "oddr" -library "oddr" -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
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set_global_assignment -entity "oddr" -library "oddr" -name IP_QSYS_MODE "UNKNOWN"
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set_global_assignment -name SYNTHESIS_ONLY_QIP ON
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set_global_assignment -entity "oddr" -library "oddr" -name IP_COMPONENT_NAME "b2Rkcg=="
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set_global_assignment -entity "oddr" -library "oddr" -name IP_COMPONENT_DISPLAY_NAME "R1BJTyBMaXRlIEludGVsIEZQR0EgSVA="
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set_global_assignment -entity "oddr" -library "oddr" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
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set_global_assignment -entity "oddr" -library "oddr" -name IP_COMPONENT_INTERNAL "Off"
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set_global_assignment -entity "oddr" -library "oddr" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
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set_global_assignment -entity "oddr" -library "oddr" -name IP_COMPONENT_VERSION "MjAuMQ=="
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set_global_assignment -entity "oddr" -library "oddr" -name IP_COMPONENT_DESCRIPTION "R1BJTyBMaXRlIEludGVsIEZQR0EgSVA="
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set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_COMPONENT_NAME "YWx0ZXJhX2dwaW9fbGl0ZQ=="
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set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_COMPONENT_DISPLAY_NAME "R1BJTyBMaXRlIEludGVsIEZQR0EgSVA="
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set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
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set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_COMPONENT_INTERNAL "Off"
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set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
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set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_COMPONENT_VERSION "MjAuMQ=="
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set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_COMPONENT_DESCRIPTION "R1BJTyBMaXRlIEludGVsIEZQR0EgSVA="
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set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWQ==::TUFYIDEw::RGV2aWNlIGZhbWlseQ=="
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set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_COMPONENT_PARAMETER "UElOX1RZUEU=::b3V0cHV0::RGF0YSBkaXJlY3Rpb24="
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set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_COMPONENT_PARAMETER "U0laRQ==::MQ==::RGF0YSB3aWR0aA=="
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set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_COMPONENT_PARAMETER "Z3VpX3RydWVfZGlmZl9idWY=::ZmFsc2U=::VXNlIHRydWUgZGlmZmVyZW50aWFsIGJ1ZmZlcg=="
|
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set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_COMPONENT_PARAMETER "Z3VpX3BzZXVkb19kaWZmX2J1Zg==::ZmFsc2U=::VXNlIHBzZXVkbyBkaWZmZXJlbnRpYWwgYnVmZmVy"
|
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set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_COMPONENT_PARAMETER "Z3VpX2J1c19ob2xk::ZmFsc2U=::VXNlIGJ1cy1ob2xkIGNpcmN1aXRyeQ=="
|
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set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_COMPONENT_PARAMETER "Z3VpX29wZW5fZHJhaW4=::ZmFsc2U=::VXNlIG9wZW4gZHJhaW4gb3V0cHV0"
|
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set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9vZV9wb3J0::ZmFsc2U=::RW5hYmxlIG9lIHBvcnQ="
|
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set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_COMPONENT_PARAMETER "Z3VpX2lvX3JlZ19tb2Rl::ZGRy::UmVnaXN0ZXIgbW9kZQ=="
|
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set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9hY2xyX3BvcnQ=::dHJ1ZQ==::RW5hYmxlIGFjbHIgcG9ydA=="
|
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set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_COMPONENT_PARAMETER "Z3VpX2Nsb2NrX2VuYWJsZQ==::ZmFsc2U=::RW5hYmxlIGluY2xvY2tlbi9vdXRjbG9ja2VuIHBvcnRz"
|
||||
set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_COMPONENT_PARAMETER "Z3VpX2ludmVydF9vdXRwdXQ=::ZmFsc2U=::SW52ZXJ0IGRpbg=="
|
||||
set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9yZWdpc3Rlcl90b19kcml2ZV9vYnVmX29l::ZmFsc2U=::VXNlIGEgc2luZ2xlIHJlZ2lzdGVyIHRvIGRyaXZlIHRoZSBvdXRwdXQgZW5hYmxlIChvZSkgc2lnbmFsIGF0IHRoZSBJL08gYnVmZmVy"
|
||||
set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9kZGlvX3JlZ190b19kcml2ZV9vZQ==::ZmFsc2U=::VXNlIERESU8gcmVnaXN0ZXJzIHRvIGRyaXZlIHRoZSBvdXRwdXQgZW5hYmxlIChvZSkgc2lnbmFsIGF0IHRoZSBJL08gYnVmZmVy"
|
||||
set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9hZHZhbmNlZF9kZHJfZmVhdHVyZXM=::ZmFsc2U=::RW5hYmxlIGFkdmFuY2VkIEREUiBmZWF0dXJlcw=="
|
||||
set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9waGFzZV9kZXRlY3Rvcl9mb3JfY2s=::ZmFsc2U=::RW5hYmxlIFBoYXNlIERldGVjdG9yIGZyb20gQ0sgbG9vcGJhY2sgc2lnbmFs"
|
||||
set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9vZV9oYWxmX2N5Y2xlX2RlbGF5::dHJ1ZQ==::QWRkIGhhbGYtY3ljbGUgZGVsYXkgdG8gT0Ugc2lnbmFs"
|
||||
set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9ocl9jbG9jaw==::ZmFsc2U=::RW5hYmxlIGhhbGYtcmF0ZSBjbG9jayBwb3J0"
|
||||
set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9pbnZlcnRfaHJfY2xvY2tfcG9ydA==::ZmFsc2U=::RW5hYmxlIGludmVydF9ocl9jbG9jayBwb3J0"
|
||||
set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_COMPONENT_PARAMETER "Z3VpX2ludmVydF9jbGtkaXZfaW5wdXRfY2xvY2s=::ZmFsc2U=::SW52ZXJ0IGNsb2NrIGRpdmlkZXIgaW5wdXQgY2xvY2s="
|
||||
set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_COMPONENT_PARAMETER "Z3VpX2ludmVydF9vdXRwdXRfY2xvY2s=::ZmFsc2U=::SW52ZXJ0IERESU8gb3V0Y2xvY2s="
|
||||
set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_COMPONENT_PARAMETER "Z3VpX2ludmVydF9vZV9pbmNsb2Nr::ZmFsc2U=::SW52ZXJ0IG91dHB1dCBlbmFibGUgKG9lKSByZWdpc3RlciBpbmNsb2Nr"
|
||||
set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_COMPONENT_PARAMETER "UkVHSVNURVJfTU9ERQ==::ZGRy::UkVHSVNURVJfTU9ERQ=="
|
||||
set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_COMPONENT_PARAMETER "QlVGRkVSX1RZUEU=::c2luZ2xlLWVuZGVk::QlVGRkVSX1RZUEU="
|
||||
set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_COMPONENT_PARAMETER "QVNZTkNfTU9ERQ==::Y2xlYXI=::QVNZTkNfTU9ERQ=="
|
||||
set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_COMPONENT_PARAMETER "U1lOQ19NT0RF::bm9uZQ==::U1lOQ19NT0RF"
|
||||
set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_COMPONENT_PARAMETER "QlVTX0hPTEQ=::ZmFsc2U=::QlVTX0hPTEQ="
|
||||
set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_COMPONENT_PARAMETER "T1BFTl9EUkFJTl9PVVRQVVQ=::ZmFsc2U=::T1BFTl9EUkFJTl9PVVRQVVQ="
|
||||
set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_COMPONENT_PARAMETER "RU5BQkxFX09FX1BPUlQ=::ZmFsc2U=::RU5BQkxFX09FX1BPUlQ="
|
||||
set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05TTEVFUF9QT1JU::ZmFsc2U=::RU5BQkxFX05TTEVFUF9QT1JU"
|
||||
set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0NMT0NLX0VOQV9QT1JU::ZmFsc2U=::RU5BQkxFX0NMT0NLX0VOQV9QT1JU"
|
||||
set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_COMPONENT_PARAMETER "U0VUX1JFR0lTVEVSX09VVFBVVFNfSElHSA==::ZmFsc2U=::U0VUX1JFR0lTVEVSX09VVFBVVFNfSElHSA=="
|
||||
set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_COMPONENT_PARAMETER "SU5WRVJUX09VVFBVVA==::ZmFsc2U=::SU5WRVJUX09VVFBVVA=="
|
||||
set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_COMPONENT_PARAMETER "SU5WRVJUX0lOUFVUX0NMT0NL::ZmFsc2U=::SU5WRVJUX0lOUFVUX0NMT0NL"
|
||||
set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_COMPONENT_PARAMETER "VVNFX09ORV9SRUdfVE9fRFJJVkVfT0U=::ZmFsc2U=::VVNFX09ORV9SRUdfVE9fRFJJVkVfT0U="
|
||||
set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_COMPONENT_PARAMETER "VVNFX0RESU9fUkVHX1RPX0RSSVZFX09F::ZmFsc2U=::VVNFX0RESU9fUkVHX1RPX0RSSVZFX09F"
|
||||
set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_COMPONENT_PARAMETER "VVNFX0FEVkFOQ0VEX0REUl9GRUFUVVJFUw==::ZmFsc2U=::VVNFX0FEVkFOQ0VEX0REUl9GRUFUVVJFUw=="
|
||||
set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_COMPONENT_PARAMETER "VVNFX0FEVkFOQ0VEX0REUl9GRUFUVVJFU19GT1JfSU5QVVRfT05MWQ==::ZmFsc2U=::VVNFX0FEVkFOQ0VEX0REUl9GRUFUVVJFU19GT1JfSU5QVVRfT05MWQ=="
|
||||
set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_COMPONENT_PARAMETER "RU5BQkxFX09FX0hBTEZfQ1lDTEVfREVMQVk=::dHJ1ZQ==::RU5BQkxFX09FX0hBTEZfQ1lDTEVfREVMQVk="
|
||||
set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_COMPONENT_PARAMETER "SU5WRVJUX0NMS0RJVl9JTlBVVF9DTE9DSw==::ZmFsc2U=::SU5WRVJUX0NMS0RJVl9JTlBVVF9DTE9DSw=="
|
||||
set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_COMPONENT_PARAMETER "RU5BQkxFX1BIQVNFX0lOVkVSVF9DVFJMX1BPUlQ=::ZmFsc2U=::RU5BQkxFX1BIQVNFX0lOVkVSVF9DVFJMX1BPUlQ="
|
||||
set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0hSX0NMT0NL::ZmFsc2U=::RU5BQkxFX0hSX0NMT0NL"
|
||||
set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_COMPONENT_PARAMETER "SU5WRVJUX09VVFBVVF9DTE9DSw==::ZmFsc2U=::SU5WRVJUX09VVFBVVF9DTE9DSw=="
|
||||
set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_COMPONENT_PARAMETER "SU5WRVJUX09FX0lOQ0xPQ0s=::ZmFsc2U=::SU5WRVJUX09FX0lOQ0xPQ0s="
|
||||
set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_COMPONENT_PARAMETER "RU5BQkxFX1BIQVNFX0RFVEVDVE9SX0ZPUl9DSw==::ZmFsc2U=::RU5BQkxFX1BIQVNFX0RFVEVDVE9SX0ZPUl9DSw=="
|
||||
|
||||
set_global_assignment -library "oddr" -name VERILOG_FILE [file join $::quartus(qip_path) "oddr.v"]
|
||||
set_global_assignment -library "oddr" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "oddr/altera_gpio_lite.sv"]
|
||||
|
||||
set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_TOOL_NAME "altera_gpio_lite"
|
||||
set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_TOOL_VERSION "20.1"
|
||||
set_global_assignment -entity "altera_gpio_lite" -library "oddr" -name IP_TOOL_ENV "mwpim"
|
||||
@@ -0,0 +1,124 @@
|
||||
// megafunction wizard: %GPIO Lite Intel FPGA IP v20.1%
|
||||
// GENERATION: XML
|
||||
// oddr.v
|
||||
|
||||
// Generated using ACDS version 20.1 711
|
||||
|
||||
`timescale 1 ps / 1 ps
|
||||
module oddr (
|
||||
input wire outclock, // outclock.export
|
||||
input wire [1:0] din, // din.export
|
||||
output wire [0:0] pad_out, // pad_out.export
|
||||
input wire aclr // aclr.export
|
||||
);
|
||||
|
||||
altera_gpio_lite #(
|
||||
.PIN_TYPE ("output"),
|
||||
.SIZE (1),
|
||||
.REGISTER_MODE ("ddr"),
|
||||
.BUFFER_TYPE ("single-ended"),
|
||||
.ASYNC_MODE ("clear"),
|
||||
.SYNC_MODE ("none"),
|
||||
.BUS_HOLD ("false"),
|
||||
.OPEN_DRAIN_OUTPUT ("false"),
|
||||
.ENABLE_OE_PORT ("false"),
|
||||
.ENABLE_NSLEEP_PORT ("false"),
|
||||
.ENABLE_CLOCK_ENA_PORT ("false"),
|
||||
.SET_REGISTER_OUTPUTS_HIGH ("false"),
|
||||
.INVERT_OUTPUT ("false"),
|
||||
.INVERT_INPUT_CLOCK ("false"),
|
||||
.USE_ONE_REG_TO_DRIVE_OE ("false"),
|
||||
.USE_DDIO_REG_TO_DRIVE_OE ("false"),
|
||||
.USE_ADVANCED_DDR_FEATURES ("false"),
|
||||
.USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY ("false"),
|
||||
.ENABLE_OE_HALF_CYCLE_DELAY ("true"),
|
||||
.INVERT_CLKDIV_INPUT_CLOCK ("false"),
|
||||
.ENABLE_PHASE_INVERT_CTRL_PORT ("false"),
|
||||
.ENABLE_HR_CLOCK ("false"),
|
||||
.INVERT_OUTPUT_CLOCK ("false"),
|
||||
.INVERT_OE_INCLOCK ("false"),
|
||||
.ENABLE_PHASE_DETECTOR_FOR_CK ("false")
|
||||
) oddr_inst (
|
||||
.outclock (outclock), // outclock.export
|
||||
.din (din), // din.export
|
||||
.pad_out (pad_out), // pad_out.export
|
||||
.aclr (aclr), // aclr.export
|
||||
.outclocken (1'b1), // (terminated)
|
||||
.inclock (1'b0), // (terminated)
|
||||
.inclocken (1'b0), // (terminated)
|
||||
.fr_clock (), // (terminated)
|
||||
.hr_clock (), // (terminated)
|
||||
.invert_hr_clock (1'b0), // (terminated)
|
||||
.phy_mem_clock (1'b0), // (terminated)
|
||||
.mimic_clock (), // (terminated)
|
||||
.dout (), // (terminated)
|
||||
.pad_io (), // (terminated)
|
||||
.pad_io_b (), // (terminated)
|
||||
.pad_in (1'b0), // (terminated)
|
||||
.pad_in_b (1'b0), // (terminated)
|
||||
.pad_out_b (), // (terminated)
|
||||
.aset (1'b0), // (terminated)
|
||||
.sclr (1'b0), // (terminated)
|
||||
.nsleep (1'b0), // (terminated)
|
||||
.oe (1'b0) // (terminated)
|
||||
);
|
||||
|
||||
endmodule
|
||||
// Retrieval info: <?xml version="1.0"?>
|
||||
//<!--
|
||||
// Generated by Altera MegaWizard Launcher Utility version 1.0
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
// ************************************************************
|
||||
// Copyright (C) 1991-2020 Altera Corporation
|
||||
// Any megafunction design, and related net list (encrypted or decrypted),
|
||||
// support information, device programming or simulation file, and any other
|
||||
// associated documentation or information provided by Altera or a partner
|
||||
// under Altera's Megafunction Partnership Program may be used only to
|
||||
// program PLD devices (but not masked PLD devices) from Altera. Any other
|
||||
// use of such megafunction design, net list, support information, device
|
||||
// programming or simulation file, or any other related documentation or
|
||||
// information is prohibited for any other purpose, including, but not
|
||||
// limited to modification, reverse engineering, de-compiling, or use with
|
||||
// any other silicon devices, unless such use is explicitly licensed under
|
||||
// a separate agreement with Altera or a megafunction partner. Title to
|
||||
// the intellectual property, including patents, copyrights, trademarks,
|
||||
// trade secrets, or maskworks, embodied in any such megafunction design,
|
||||
// net list, support information, device programming or simulation file, or
|
||||
// any other related documentation or information provided by Altera or a
|
||||
// megafunction partner, remains with Altera, the megafunction partner, or
|
||||
// their respective licensors. No other licenses, including any licenses
|
||||
// needed under any third party's intellectual property, are provided herein.
|
||||
//-->
|
||||
// Retrieval info: <instance entity-name="altera_gpio_lite" version="20.1" >
|
||||
// Retrieval info: <generic name="DEVICE_FAMILY" value="MAX 10" />
|
||||
// Retrieval info: <generic name="PIN_TYPE" value="output" />
|
||||
// Retrieval info: <generic name="SIZE" value="1" />
|
||||
// Retrieval info: <generic name="gui_true_diff_buf" value="false" />
|
||||
// Retrieval info: <generic name="gui_pseudo_diff_buf" value="false" />
|
||||
// Retrieval info: <generic name="gui_bus_hold" value="false" />
|
||||
// Retrieval info: <generic name="gui_open_drain" value="false" />
|
||||
// Retrieval info: <generic name="gui_enable_oe_port" value="false" />
|
||||
// Retrieval info: <generic name="gui_enable_nsleep_port" value="false" />
|
||||
// Retrieval info: <generic name="gui_io_reg_mode" value="ddr" />
|
||||
// Retrieval info: <generic name="gui_enable_aclr_port" value="true" />
|
||||
// Retrieval info: <generic name="gui_enable_aset_port" value="false" />
|
||||
// Retrieval info: <generic name="gui_enable_sclr_port" value="false" />
|
||||
// Retrieval info: <generic name="gui_set_registers_to_power_up_high" value="false" />
|
||||
// Retrieval info: <generic name="gui_clock_enable" value="false" />
|
||||
// Retrieval info: <generic name="gui_invert_output" value="false" />
|
||||
// Retrieval info: <generic name="gui_invert_input_clock" value="false" />
|
||||
// Retrieval info: <generic name="gui_use_register_to_drive_obuf_oe" value="false" />
|
||||
// Retrieval info: <generic name="gui_use_ddio_reg_to_drive_oe" value="false" />
|
||||
// Retrieval info: <generic name="gui_use_advanced_ddr_features" value="false" />
|
||||
// Retrieval info: <generic name="gui_enable_phase_detector_for_ck" value="false" />
|
||||
// Retrieval info: <generic name="gui_enable_oe_half_cycle_delay" value="true" />
|
||||
// Retrieval info: <generic name="gui_enable_hr_clock" value="false" />
|
||||
// Retrieval info: <generic name="gui_enable_invert_hr_clock_port" value="false" />
|
||||
// Retrieval info: <generic name="gui_invert_clkdiv_input_clock" value="false" />
|
||||
// Retrieval info: <generic name="gui_invert_output_clock" value="false" />
|
||||
// Retrieval info: <generic name="gui_invert_oe_inclock" value="false" />
|
||||
// Retrieval info: <generic name="gui_use_hardened_ddio_input_registers" value="false" />
|
||||
// Retrieval info: </instance>
|
||||
// IPFS_FILES : oddr.vo
|
||||
// RELATED_FILES: oddr.v, altera_gpio_lite.sv
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,12 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<!DOCTYPE pinplan>
|
||||
<pinplan intended_family="MAX 10" variation_name="pll" megafunction_name="ALTPLL" specifies="all_ports">
|
||||
<global>
|
||||
<pin name="inclk0" direction="input" scope="external" source="clock" />
|
||||
<pin name="c0" direction="output" scope="external" source="clock" />
|
||||
<pin name="c1" direction="output" scope="external" source="clock" />
|
||||
<pin name="c2" direction="output" scope="external" source="clock" />
|
||||
<pin name="locked" direction="output" scope="external" />
|
||||
|
||||
</global>
|
||||
</pinplan>
|
||||
@@ -0,0 +1,5 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
|
||||
set_global_assignment -name IP_TOOL_VERSION "20.1"
|
||||
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
|
||||
@@ -0,0 +1,368 @@
|
||||
// megafunction wizard: %ALTPLL%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: altpll
|
||||
|
||||
// ============================================================
|
||||
// File Name: pll.v
|
||||
// Megafunction Name(s):
|
||||
// altpll
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// altera_mf
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 20.1.0 Build 711 06/05/2020 SJ Standard Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
//Your use of Intel Corporation's design tools, logic functions
|
||||
//and other software and tools, and any partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Intel Program License
|
||||
//Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
//the Intel FPGA IP License Agreement, or other applicable license
|
||||
//agreement, including, without limitation, that your use is for
|
||||
//the sole purpose of programming logic devices manufactured by
|
||||
//Intel and sold by Intel or its authorized distributors. Please
|
||||
//refer to the applicable agreement for further details, at
|
||||
//https://fpgasoftware.intel.com/eula.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module pll (
|
||||
inclk0,
|
||||
c0,
|
||||
c1,
|
||||
c2,
|
||||
locked);
|
||||
|
||||
input inclk0;
|
||||
output c0;
|
||||
output c1;
|
||||
output c2;
|
||||
output locked;
|
||||
|
||||
wire [0:0] sub_wire2 = 1'h0;
|
||||
wire [4:0] sub_wire3;
|
||||
wire sub_wire7;
|
||||
wire sub_wire0 = inclk0;
|
||||
wire [1:0] sub_wire1 = {sub_wire2, sub_wire0};
|
||||
wire [2:2] sub_wire6 = sub_wire3[2:2];
|
||||
wire [1:1] sub_wire5 = sub_wire3[1:1];
|
||||
wire [0:0] sub_wire4 = sub_wire3[0:0];
|
||||
wire c0 = sub_wire4;
|
||||
wire c1 = sub_wire5;
|
||||
wire c2 = sub_wire6;
|
||||
wire locked = sub_wire7;
|
||||
|
||||
altpll altpll_component (
|
||||
.inclk (sub_wire1),
|
||||
.clk (sub_wire3),
|
||||
.locked (sub_wire7),
|
||||
.activeclock (),
|
||||
.areset (1'b0),
|
||||
.clkbad (),
|
||||
.clkena ({6{1'b1}}),
|
||||
.clkloss (),
|
||||
.clkswitch (1'b0),
|
||||
.configupdate (1'b0),
|
||||
.enable0 (),
|
||||
.enable1 (),
|
||||
.extclk (),
|
||||
.extclkena ({4{1'b1}}),
|
||||
.fbin (1'b1),
|
||||
.fbmimicbidir (),
|
||||
.fbout (),
|
||||
.fref (),
|
||||
.icdrclk (),
|
||||
.pfdena (1'b1),
|
||||
.phasecounterselect ({4{1'b1}}),
|
||||
.phasedone (),
|
||||
.phasestep (1'b1),
|
||||
.phaseupdown (1'b1),
|
||||
.pllena (1'b1),
|
||||
.scanaclr (1'b0),
|
||||
.scanclk (1'b0),
|
||||
.scanclkena (1'b1),
|
||||
.scandata (1'b0),
|
||||
.scandataout (),
|
||||
.scandone (),
|
||||
.scanread (1'b0),
|
||||
.scanwrite (1'b0),
|
||||
.sclkout0 (),
|
||||
.sclkout1 (),
|
||||
.vcooverrange (),
|
||||
.vcounderrange ());
|
||||
defparam
|
||||
altpll_component.bandwidth_type = "AUTO",
|
||||
altpll_component.clk0_divide_by = 2,
|
||||
altpll_component.clk0_duty_cycle = 50,
|
||||
altpll_component.clk0_multiply_by = 1,
|
||||
altpll_component.clk0_phase_shift = "0",
|
||||
altpll_component.clk1_divide_by = 2,
|
||||
altpll_component.clk1_duty_cycle = 50,
|
||||
altpll_component.clk1_multiply_by = 5,
|
||||
altpll_component.clk1_phase_shift = "0",
|
||||
altpll_component.clk2_divide_by = 5,
|
||||
altpll_component.clk2_duty_cycle = 50,
|
||||
altpll_component.clk2_multiply_by = 2,
|
||||
altpll_component.clk2_phase_shift = "0",
|
||||
altpll_component.compensate_clock = "CLK0",
|
||||
altpll_component.inclk0_input_frequency = 10000,
|
||||
altpll_component.intended_device_family = "MAX 10",
|
||||
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
|
||||
altpll_component.lpm_type = "altpll",
|
||||
altpll_component.operation_mode = "NORMAL",
|
||||
altpll_component.pll_type = "AUTO",
|
||||
altpll_component.port_activeclock = "PORT_UNUSED",
|
||||
altpll_component.port_areset = "PORT_UNUSED",
|
||||
altpll_component.port_clkbad0 = "PORT_UNUSED",
|
||||
altpll_component.port_clkbad1 = "PORT_UNUSED",
|
||||
altpll_component.port_clkloss = "PORT_UNUSED",
|
||||
altpll_component.port_clkswitch = "PORT_UNUSED",
|
||||
altpll_component.port_configupdate = "PORT_UNUSED",
|
||||
altpll_component.port_fbin = "PORT_UNUSED",
|
||||
altpll_component.port_inclk0 = "PORT_USED",
|
||||
altpll_component.port_inclk1 = "PORT_UNUSED",
|
||||
altpll_component.port_locked = "PORT_USED",
|
||||
altpll_component.port_pfdena = "PORT_UNUSED",
|
||||
altpll_component.port_phasecounterselect = "PORT_UNUSED",
|
||||
altpll_component.port_phasedone = "PORT_UNUSED",
|
||||
altpll_component.port_phasestep = "PORT_UNUSED",
|
||||
altpll_component.port_phaseupdown = "PORT_UNUSED",
|
||||
altpll_component.port_pllena = "PORT_UNUSED",
|
||||
altpll_component.port_scanaclr = "PORT_UNUSED",
|
||||
altpll_component.port_scanclk = "PORT_UNUSED",
|
||||
altpll_component.port_scanclkena = "PORT_UNUSED",
|
||||
altpll_component.port_scandata = "PORT_UNUSED",
|
||||
altpll_component.port_scandataout = "PORT_UNUSED",
|
||||
altpll_component.port_scandone = "PORT_UNUSED",
|
||||
altpll_component.port_scanread = "PORT_UNUSED",
|
||||
altpll_component.port_scanwrite = "PORT_UNUSED",
|
||||
altpll_component.port_clk0 = "PORT_USED",
|
||||
altpll_component.port_clk1 = "PORT_USED",
|
||||
altpll_component.port_clk2 = "PORT_USED",
|
||||
altpll_component.port_clk3 = "PORT_UNUSED",
|
||||
altpll_component.port_clk4 = "PORT_UNUSED",
|
||||
altpll_component.port_clk5 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena0 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena1 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena2 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena3 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena4 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena5 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk0 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk1 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk2 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk3 = "PORT_UNUSED",
|
||||
altpll_component.self_reset_on_loss_lock = "OFF",
|
||||
altpll_component.width_clock = 5;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
|
||||
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
|
||||
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "2"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "2"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "250.000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "40.000000"
|
||||
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||||
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
|
||||
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "100.000"
|
||||
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
|
||||
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
|
||||
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
|
||||
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "5"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "40.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
|
||||
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
|
||||
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
|
||||
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
|
||||
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
|
||||
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
|
||||
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
|
||||
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK3 STRING "0"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK4 STRING "0"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
|
||||
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
|
||||
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"
|
||||
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "5"
|
||||
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "5"
|
||||
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "2"
|
||||
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "10000"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
|
||||
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
|
||||
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
|
||||
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
|
||||
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
|
||||
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
|
||||
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||||
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
|
||||
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
|
||||
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
||||
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
|
||||
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
// Retrieval info: CBX_MODULE_PREFIX: ON
|
||||
Reference in New Issue
Block a user