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fpga: x400: zbx: Improve Lattice make flow

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Original-commit: fa8559bb0f334d80e08798d415117cedf86be923
This commit is contained in:
Max Köhler
2024-03-05 20:07:50 -06:00
committed by Wade Fife
parent e2c442ab8c
commit 7be838b24c
5 changed files with 26 additions and 14 deletions
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top/x400/dboards/zbx/cpld/lattice/zbx_top_cpld.ldf
+3 -3
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@@ -27,7 +27,7 @@
<Source name="../../../../../../lib/control/synchronizer_impl.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../../../../cpld/reconfig_engine.v" type="Verilog" type_short="Verilog">
<Source name="../../../../cpld/common/reconfig_engine.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../../../ctrlport_byte_deserializer.v" type="Verilog" type_short="Verilog">
@@ -45,10 +45,10 @@
<Source name="../../../../../../lib/wb_spi/rtl/verilog/spi_top.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../../../../cpld/spi_slave.v" type="Verilog" type_short="Verilog">
<Source name="../../../../cpld/common/spi_slave.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../../../../cpld/spi_slave_to_ctrlport_master.v" type="Verilog" type_short="Verilog">
<Source name="../../../../cpld/common/spi_slave_to_ctrlport_master.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../../../../../../lib/rfnoc/utils/ctrlport_window.v" type="Verilog" type_short="Verilog">