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fpga: x400: zbx: Improve Lattice make flow

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Original-commit: fa8559bb0f334d80e08798d415117cedf86be923
This commit is contained in:
Max Köhler
2024-03-05 20:07:50 -06:00
committed by Wade Fife
parent e2c442ab8c
commit 7be838b24c
5 changed files with 26 additions and 14 deletions
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top/x400/dboards/zbx/cpld/Makefile
+6 -8
View File
@@ -13,11 +13,10 @@
##
##Output:
## build/<device-id>/usrp_zbx_cpld_10m04.pof: Bitstream to use with JTAG programmer
## build/<device-id>/usrp_zbx_cpld_10m04.svf: Bitstream to use with PS JTAG engine (background programming)
## build/<device-id>/usrp_zbx_cpld_10m04.rpd: Bitstream to use via reconfig engine
## build/<device-id>/usrp_zbx_cpld_10m04_isp_off.svf: Bitstream to use with JTAG test points (initial programming)
## build/<device-id>/usrp_zbx_cpld_10m04_isp_off.svf: Bitstream to use with JTAG
## build/<device-id>/usrp_zbx_cpld_xo3lf.jed: Bitstream to use with JTAG programmer
## build/<device-id>/usrp_zbx_cpld_xo3lf.svf: Bitstream to use with PS JTAG engine (background programming)
## build/<device-id>/usrp_zbx_cpld_xo3lf.svf: Bitstream to use with JTAG
# Definitions
10M04_ID = "10M04SAU324I7G"
@@ -53,11 +52,10 @@ ifeq ($(TARGET),bin)
cp build-$@/output_files/$(TOP)_isp_off.svf build/$(1)_10m04_isp_off.svf; \
cp build-$@/output_files/$(TOP)_isp_on.svf build/$(1)_10m04.svf; \
cp build-$@/output_files/$(TOP)_converted_cfm0_auto.rpd build/$(1)_10m04.rpd; \
echo -ne "\n\n---- Make: MB CPLD ready!\n"; \
echo -ne "\n\n---- Make: ZBX CPLD ready!\n"; \
echo -ne " Use build/$(1).pof via JTAG programmer or\n"; \
echo -ne " build/$(1).svf (ISP on) via PS JTAG-engine (background programming) or\n"; \
echo -ne " build/$(1).rpd via reconfig engine or\n"; \
echo -ne " build/$(1)_isp_off.svf via JTAG test points (initial programming)\n";
echo -ne " build/$(1)_isp_off.svf via JTAG\n";
else
post_quar_build = @echo "Skipping bitfile export."
endif
@@ -71,8 +69,8 @@ ifeq ($(TARGET),bin)
mkdir -p build/; \
echo "Exporting bitstream files..."; \
cp build-$@/$(2)/$(TOP)_$(2).svf build/$(1)_xo3lf.svf; \
echo -ne "\n\n---- Make: MB CPLD ready!\n"; \
echo -ne " Use build/$(1)_xo3lf.svf via PS JTAG-engine \n";
echo -ne "\n\n---- Make: ZBX CPLD ready!\n"; \
echo -ne " Use build/$(1)_xo3lf.svf\n";
else
post_dmd_build = @echo "Skipping bitfile export."
endif
top/x400/dboards/zbx/cpld/Makefile.zbx_cpld.inc
+6 -1
View File
@@ -33,6 +33,11 @@ REGS_PY_FILE=$(PROJECT_DIR)/../../../../../../../host/lib/ic_reg_maps/gen_zbx_cp
INIT_FILES_DIR=$(PROJECT_DIR)/register_endpoints/memory_init_files/
REGS_PY_MODULE=$(INIT_FILES_DIR)/zbx_cpld_regs_t.py
.init_files_prereqs:
@echo "BUILDER: Checking tools..."
@echo -n "* "; python3 --version || (echo "ERROR: Python not found in environment. Please install it"; exit 1;)
@echo -n "* "; python3 -c "import mako" || (echo "ERROR: Python package mako not installed. Please install it"; exit 1;)
$(REGS_PY_MODULE): $(REGS_PY_FILE)
@python3 $(REGS_PY_FILE) $(REGS_PY_MODULE)
@@ -42,7 +47,7 @@ INIT_FILES := $(INIT_FILES_DIR)/rx0_path_defaults.hex
$(INIT_FILES): $(REGS_PY_MODULE) $(INIT_FILES_DIR)/gen_defaults.py
@python3 $(INIT_FILES_DIR)/gen_defaults.py
cpld_defaults: .prereqs $(INIT_FILES)
cpld_defaults: .init_files_prereqs $(INIT_FILES)
@echo "Initialization files DONE ..."
bin: .prereqs
top/x400/dboards/zbx/cpld/lattice/zbx_top_cpld.ldf
+3 -3
View File
@@ -27,7 +27,7 @@
<Source name="../../../../../../lib/control/synchronizer_impl.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../../../../cpld/reconfig_engine.v" type="Verilog" type_short="Verilog">
<Source name="../../../../cpld/common/reconfig_engine.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../../../ctrlport_byte_deserializer.v" type="Verilog" type_short="Verilog">
@@ -45,10 +45,10 @@
<Source name="../../../../../../lib/wb_spi/rtl/verilog/spi_top.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../../../../cpld/spi_slave.v" type="Verilog" type_short="Verilog">
<Source name="../../../../cpld/common/spi_slave.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../../../../cpld/spi_slave_to_ctrlport_master.v" type="Verilog" type_short="Verilog">
<Source name="../../../../cpld/common/spi_slave_to_ctrlport_master.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../../../../../../lib/rfnoc/utils/ctrlport_window.v" type="Verilog" type_short="Verilog">