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fpga: tools: Fix ModelSim return status

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Original-commit: 05137529261bf9eae2a8b72cdf67e86a8ff96927
This commit is contained in:
Wade Fife
2020-06-18 15:26:07 -05:00
parent 55881469ac
commit 7b1174ffd9
2 changed files with 12 additions and 5 deletions
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tools/scripts/launch_vlint.sh
+6 -3
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@@ -126,21 +126,24 @@ if [[ -n "$SV_FILES" ]]; then
vlog $SVLOG_ARGS -sv -f svlogarglist.txt 2>&1 | while IFS= read -r line; do
print_color $line
done
if [ ${PIPESTATUS[0]} -ne 0 ]; then exit ${PIPESTATUS[0]}; fi
exit_status=${PIPESTATUS[0]}
if [ ${exit_status} -ne 0 ]; then exit ${exit_status}; fi
fi
if [[ -n "$V_FILES" ]]; then
echo "* Compiling Verilog"
vlog $VLOG_ARGS -f vlogarglist.txt 2>&1 | while IFS= read -r line; do
print_color $line
done
if [ ${PIPESTATUS[0]} -ne 0 ]; then exit ${PIPESTATUS[0]}; fi
exit_status=${PIPESTATUS[0]}
if [ ${exit_status} -ne 0 ]; then exit ${exit_status}; fi
fi
if [[ -n "$VHD_FILES" ]]; then
echo "* Compiling VHDL"
vcom $VHDL_ARGS -f vcomarglist.txt 2>&1 | while IFS= read -r line; do
print_color $line
done
if [ ${PIPESTATUS[0]} -ne 0 ]; then exit ${PIPESTATUS[0]}; fi
exit_status=${PIPESTATUS[0]}
if [ ${exit_status} -ne 0 ]; then exit ${exit_status}; fi
fi