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fpga: lib: extend wb_spi ability to limit transmission length

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Original-commit: 427a3939da459d6fb786a274ee04e28c950b71fd
This commit is contained in:
Max Köhler
2020-06-04 14:46:19 -05:00
committed by Wade Fife
parent cb90fe98ef
commit 750317582d
1 changed files with 9 additions and 3 deletions
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lib/wb_spi/rtl/verilog/spi_defines.v
+9 -3
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@@ -62,12 +62,18 @@
`endif `endif
// //
// Maximum nuber of bits that can be send/received at once. // Maximum number of bits that can be send/received at once.
// Use SPI_MAX_CHAR for fine tuning the exact number, when using // Use SPI_MAX_CHAR for fine tuning the exact number, when using
// SPI_MAX_CHAR_32, SPI_MAX_CHAR_24, SPI_MAX_CHAR_16, SPI_MAX_CHAR_8. // SPI_MAX_CHAR_32, SPI_MAX_CHAR_24, SPI_MAX_CHAR_16, SPI_MAX_CHAR_8.
// //
`ifndef SPI_MAX_CHAR_64 `ifndef SPI_MAX_CHAR_8
`define SPI_MAX_CHAR_128 `ifndef SPI_MAX_CHAR_16
`ifndef SPI_MAX_CHAR_32
`ifndef SPI_MAX_CHAR_64
`define SPI_MAX_CHAR_128
`endif
`endif
`endif
`endif `endif
//`define SPI_MAX_CHAR_64 //`define SPI_MAX_CHAR_64
//`define SPI_MAX_CHAR_32 //`define SPI_MAX_CHAR_32