From 750317582d85c665674157e49ede1d75ff1623a3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Max=20K=C3=B6hler?= Date: Fri, 22 May 2020 22:01:13 +0200 Subject: [PATCH] fpga: lib: extend wb_spi ability to limit transmission length Original-commit: 427a3939da459d6fb786a274ee04e28c950b71fd --- lib/wb_spi/rtl/verilog/spi_defines.v | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/lib/wb_spi/rtl/verilog/spi_defines.v b/lib/wb_spi/rtl/verilog/spi_defines.v index 28b4f2f..2b10e68 100644 --- a/lib/wb_spi/rtl/verilog/spi_defines.v +++ b/lib/wb_spi/rtl/verilog/spi_defines.v @@ -62,12 +62,18 @@ `endif // -// Maximum nuber of bits that can be send/received at once. +// Maximum number of bits that can be send/received at once. // Use SPI_MAX_CHAR for fine tuning the exact number, when using // SPI_MAX_CHAR_32, SPI_MAX_CHAR_24, SPI_MAX_CHAR_16, SPI_MAX_CHAR_8. // -`ifndef SPI_MAX_CHAR_64 - `define SPI_MAX_CHAR_128 +`ifndef SPI_MAX_CHAR_8 + `ifndef SPI_MAX_CHAR_16 + `ifndef SPI_MAX_CHAR_32 + `ifndef SPI_MAX_CHAR_64 + `define SPI_MAX_CHAR_128 + `endif + `endif + `endif `endif //`define SPI_MAX_CHAR_64 //`define SPI_MAX_CHAR_32