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Removed copy of FPGA source files.

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Original-commit: fd3e84941de463fa1a7ebab0a69515b4bf2614cd
This commit is contained in:
Martin Braun
2014-10-07 11:25:20 +02:00
parent 56e84828fe
commit 74893643ca
2415 changed files with 0 additions and 1492030 deletions
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lib/simple_gemac/flow_ctrl_tx.v
-44
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@@ -1,44 +0,0 @@
//
// Copyright 2011 Ettus Research LLC
//
// TX side of flow control -- when other side sends PAUSE, we wait
module flow_ctrl_tx
(input rst,
input tx_clk,
//host processor
input tx_pause_en,
// From MAC_rx_ctrl
input [15:0] pause_quanta,
input pause_quanta_val,
// MAC_tx_ctrl
output pause_apply,
input paused);
// ******************************************************************************
// Inhibit our TX from transmitting because they sent us a PAUSE frame
// ******************************************************************************
// Pauses are in units of 512 bit times, or 64 bytes/clock cycles, and can be
// as big as 16 bits, so 22 bits are needed for the counter
reg [15+6:0] pause_quanta_counter;
reg pqval_d1, pqval_d2;
always @(posedge tx_clk) pqval_d1 <= pause_quanta_val;
always @(posedge tx_clk) pqval_d2 <= pqval_d1;
always @ (posedge tx_clk or posedge rst)
if (rst)
pause_quanta_counter <= 0;
else if (pqval_d1 & ~pqval_d2)
pause_quanta_counter <= {pause_quanta, 6'b0};
else if((pause_quanta_counter!=0) & paused)
pause_quanta_counter <= pause_quanta_counter - 1;
assign pause_apply = tx_pause_en & (pause_quanta_counter != 0);
endmodule // flow_ctrl