Removed copy of FPGA source files.

Original-commit: fd3e84941de463fa1a7ebab0a69515b4bf2614cd
2014-10-07 11:25:20 +02:00
parent 56e84828fe
commit 74893643ca
2415 changed files with 0 additions and 1492030 deletions
@@ -1,23 +0,0 @@
-#
-# Copyright 2013 Ettus Research LLC
-#
-
-##################################################
-# Packet Processing Sources
-##################################################
-PACKET_PROC_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/packet_proc/, \
-eth_dispatch.v \
-ip_hdr_checksum.v \
-vrlp_eth_framer.v \
-chdr_eth_framer.v \
-eth_interface.v \
-vrlp_to_compressed_vita.v \
-compressed_vita_to_vrlp.v \
-source_flow_control.v \
-cvita_insert_tlast.v \
-cvita_dest_lookup.v \
-cvita_chunker.v \
-cvita_dechunker.v \
-axis_packet_debug.v \
-cvita_packet_debug.v \
-))