fpga: lib: Add axis_pkt_throttle.sv
Original-commit: f8f93ced23cf3ce0a3ba4339e7fa4ab0c598654d
This commit is contained in:
Wade Fife
@@ -34,4 +34,5 @@ axis_downsizer.v \
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axis_width_conv.v \
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axis_split.v \
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axis_packetize.v \
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axis_pkt_throttle.sv \
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))
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@@ -0,0 +1,179 @@
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//
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// Copyright 2023 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: axis_pkt_throttle
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//
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// Description:
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//
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// This module takes in AXI-Stream and outputs the same stream, inserting
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// gaps between packets in order to maintain a specific data rate. The amount
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// of time between packets is controlled in such a way that the length of a
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// packet divided by the time between the start of that packet and the next
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// does not exceed some rate R.
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//
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// This module does NOT insert stalls within a packet, only between packets,
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// so the peak data rate is not restricted and packet contiguity is not
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// affected. Also, the average data rate could be slightly higher than the
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// configured rate due to rounding error (within a single clock cycle per
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// packet).
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//
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// The "throttle" input port controls the rate. In order to set the rate to
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// R, where R is a fraction in the range (0,1], set throttle (T) using the
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// formula T = (1/R)-1. In other words, R = 1/(T+1).
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//
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// The "throttle" input is represented as an unsigned fixed-point value with
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// THROTTLE_W/2 whole bits and THROTTLE_W/2 fractional bits (UQn.n format).
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// Throttle is therefore in the range [0,1).
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//
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// For example, if THROTTLE_W is 8 bits then throttle is in UQ4.4 format (4
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// whole bits and 4 fractional bits). In this case, a throttle value of 0
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// corresponds to a rate of 1/(0+1) = 1.0, which is 100% or full throttle. A
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// throttle value of 15.9375 (i.e., 0xFF, or the max value) corresponds to a
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// rate of 1/(15.9375+1) = 0.05904059, or 5.9% of the maximum rate.
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//
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// The throttle input is sampled between packets. Changing the throttle
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// during a packet, or before its inserted stall time has elapsed, has no
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// effect until the next packet.
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//
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// Parameters:
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//
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// THROTTLE_W : Width of the throttle input in bits.
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// DATA_W : Width of data bus for AXI-Stream in bits.
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// MTU : The maximum supported packet length is 2**MTU.
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//
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`default_nettype none
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module axis_pkt_throttle #(
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parameter int THROTTLE_W = 8,
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parameter int DATA_W = 64,
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parameter int MTU = 10
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) (
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input wire clk,
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input wire rst,
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input wire [THROTTLE_W-1:0] throttle,
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// Input AXI-Stream
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input wire [ DATA_W-1:0] i_tdata,
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input wire i_tlast,
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input wire i_tvalid,
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output wire i_tready,
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// Output AXI-Stream
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output wire [ DATA_W-1:0] o_tdata,
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output wire o_tlast,
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output wire o_tvalid,
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input wire o_tready
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);
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//---------------------------------------------------------------------------
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// Throttle Control Logic
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//---------------------------------------------------------------------------
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//
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// This logic monitors the data flow and determines when we should pass data
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// through and when we should stall in order to limit the data rate.
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//
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//---------------------------------------------------------------------------
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// Length of the fractional part of our fixed-point throttle and count.
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localparam int FRAC_W = THROTTLE_W/2;
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// Length of the whole-number part of our fixed-point throttle.
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localparam int WHOLE_W = THROTTLE_W - FRAC_W;
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// Width of an unsigned fixed-point value to track the amount of time to
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// ensure that we have between the starts of packets. This must be large
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// enough to store (2**MTU) * (2**THROTTLE_W-1).
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localparam int TIME_W = MTU + THROTTLE_W;
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// Width of an unsigned counter to track time between packets. Same as
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// TIME_W, but the whole-number part.
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localparam int COUNT_W = TIME_W - FRAC_W;
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// Compute the minimum count value we can have and still guarantee that the
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// next stall time adjustment won't cause underflow.
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localparam longint MIN_COUNT = -(2**TIME_W) + (2**THROTTLE_W-1);
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// Fixed-point accumulator that tracks amount of time to stall between
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// packets. We add an extra bit for the sign since this value can be negative.
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logic signed [TIME_W:0] stall_time;
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// Counter to track the whole number of clock cycles to stall.
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logic [COUNT_W-1:0] wait_count;
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// Flag to indicate if underflow occurred and our count can't be trusted.
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logic underflow;
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// Register to control the flow of packets through this module. When 1, data
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// flow is gated (stopped).
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logic gate = 1'b0;
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// Start of packet flag.
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logic sop = 1'b1;
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always_ff @(posedge clk) begin : throttle_control
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if (gate) begin
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wait_count <= wait_count-1;
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gate <= (wait_count > 1);
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// Update stall_time for next packet, in case throttle changes.
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stall_time <= throttle;
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end else begin
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if (i_tvalid && o_tready) begin
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if (i_tlast) begin
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sop <= 1;
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// End of the packet. Start stalling, if needed, and reset for the
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// next packet.
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if (!underflow && !stall_time[TIME_W]) begin
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// No underflow and stall_time is non-negative, so start stalling
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// the accumulated amount.
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wait_count <= stall_time[FRAC_W+:COUNT_W];
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gate <= (stall_time[FRAC_W+:COUNT_W] != 0);
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end else begin
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// We underflowed or stall_time was negative, so don't stall.
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wait_count <= 0;
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gate <= 0;
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end
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// Reset for next packet
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underflow <= 0;
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stall_time <= throttle;
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end else begin
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// A transfer is happening this cycle. Update stall time. Note that
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// overflow is not possible as long as the MTU is honored.
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stall_time <= stall_time + throttle;
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sop <= 0;
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end
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end else begin
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if (sop) begin
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// We're in between packets. Update stall_time for next packet, in
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// case throttle changes.
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stall_time <= throttle;
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end else begin
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// An idle cycle (no transfer) is occurring this cycle so subtract
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// 1.0 from our stall time. We must check for underflow since there
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// is no limit to the number of idle cycles we might see.
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stall_time <= stall_time - (1 << FRAC_W);
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if (stall_time < MIN_COUNT) begin
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underflow <= 1;
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end
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end
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end
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end
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if (rst) begin
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sop <= 1;
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stall_time <= 0;
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wait_count <= 'X; // Don't care
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gate <= 0;
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underflow <= 0;
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end
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end : throttle_control
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//---------------------------------------------------------------------------
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// Data Pass-Through
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//---------------------------------------------------------------------------
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assign o_tdata = i_tdata;
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assign o_tlast = i_tlast;
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assign o_tvalid = i_tvalid & ~gate;
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assign i_tready = o_tready & ~gate;
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endmodule : axis_pkt_throttle
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`default_nettype wire
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