fpga: lib: Modify for loop to Verilog 2001 syntax

This changes the for loop to use the generate keyword, making it
compatible with Verilog 2001. This allows tools that only support
Verilog 2001 to use this file (e.g., Intel Quartus).


Original-commit: b92597e1c9b6f09d5e62e55a60e33c04d437a50a

lib/rfnoc/utils/ctrlport_decoder_param.v

@@ -94,6 +94,7 @@ module ctrlport_decoder_param #(
 
   wire [NUM_SLAVES-1:0] dec_mask;  // Address decoder mask
 
+  generate
     genvar i;
 
     for (i = 0; i < NUM_SLAVES; i = i+1) begin : gen_dec_mask
@@ -132,7 +133,7 @@ module ctrlport_decoder_param #(
         end
       end
     end
-
+  endgenerate
 
   //---------------------------------------------------------------------------
   // Decode the responses