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fpga: Added FPGA code for X300 MIMO alignment bugfix

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Original-commit: 3347e831f002da769632dfe0c70ea17c2d749a8a
This commit is contained in:
Ashish Chaudhari
2014-08-19 12:05:46 -07:00
parent 85ad83d8d3
commit 6b7004c311
5 changed files with 22 additions and 50 deletions
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top/x300/capture_ddrlvds.v
+10 -44
View File
@@ -1,25 +1,26 @@
//
// Copyright 2011 Ettus Research LLC
// Copyright 2011-2014 Ettus Research LLC
//
// The two clocks are aligned externally in order to eliminate the need for a FIFO.
// A FIFO cannot be used to transition between clock domains because it can cause
// alignment issues between the output of multiple modules.
module capture_ddrlvds
#(parameter WIDTH=7,
parameter X300=0)
(input clk,
input reset,
input ssclk_p,
input ssclk_n,
input [WIDTH-1:0] in_p,
input [WIDTH-1:0] in_n,
output [(2*WIDTH)-1:0] out);
output reg [(2*WIDTH)-1:0] out);
wire [WIDTH-1:0] ddr_dat;
wire ssclk;
wire [(2*WIDTH)-1:0] out_pre1;
wire ssclk_bufio1, ssclk_bufio2, ssclk_bufr, ssclk_bufmr;
reg [(2*WIDTH)-1:0] out_pre2;
wire ssclk_bufio1, ssclk_bufio2, ssclk_bufmr;
IBUFGDS #(.DIFF_TERM("TRUE"))
clkbuf (.O(ssclk), .I(ssclk_p), .IB(ssclk_n));
@@ -33,20 +34,12 @@ module capture_ddrlvds
.I(ssclk_bufmr),
.O(ssclk_bufio1)
);
BUFIO clkbufio2 (
.I(ssclk_bufmr),
.O(ssclk_bufio2)
);
BUFR
#(.SIM_DEVICE("7SERIES"),
.BUFR_DIVIDE("BYPASS"))
clkbufr (
.I(ssclk_bufmr),
.O(ssclk_bufr)
);
genvar i;
generate
@@ -68,34 +61,7 @@ module capture_ddrlvds
end
endgenerate
reg rd_en;
wire full, empty, almost_empty;
input_sample_fifo input_sample_fifo_i
(
.rst(reset), // input rst
.wr_clk(ssclk_bufr), // input wr_clk
.rd_clk(clk), // input rd_clk
.din(out_pre1), // input [27 : 0] din
.wr_en(1'b1), // input wr_en
.rd_en(rd_en), // input rd_en
.dout(out), // output [27 : 0] dout
.full(full), // output full
.empty(empty), // output empty
.almost_empty(almost_empty) // output almost_empty
);
always @(posedge clk) begin
if (reset)
rd_en <= 0;
else if (~almost_empty)
rd_en <= 1;
else if (empty)
rd_en <= 0;
end
always @(posedge clk)
{out, out_pre2} <= {out_pre2, out_pre1};
endmodule // capture_ddrlvds