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fpga: Added FPGA code for X300 MIMO alignment bugfix

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Original-commit: 3347e831f002da769632dfe0c70ea17c2d749a8a
This commit is contained in:
Ashish Chaudhari
2014-08-19 12:05:46 -07:00
parent 85ad83d8d3
commit 6b7004c311
5 changed files with 22 additions and 50 deletions
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top/x300/Makefile.x300.inc
+4 -3
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@@ -49,7 +49,7 @@ synthesis_tool "XST (VHDL/Verilog)" \
simulator "ISim (VHDL/Verilog)" \
"Preferred Language" "Verilog" \
"Enable Message Filtering" FALSE \
"Display Incremental Messages" FALSE
"Display Incremental Messages" FALSE
##################################################
# Sources
@@ -142,7 +142,8 @@ MAP_PROPERTIES = \
"Map Effort Level" High \
"Extra Effort" Normal \
"Perform Timing-Driven Packing and Placement" TRUE \
"Enable Multi-Threading 2"
"Enable Multi-Threading 2" \
"Starting Placer Cost Table (1-100)" $$(( $$RANDOM % 100 + 1 ))
#"Map to Input Functions" 4 \
PLACE_ROUTE_PROPERTIES = \
@@ -160,6 +161,6 @@ GEN_PROG_FILE_PROPERTIES = \
"Done (Output Events)" 5 \
"Enable Bitstream Compression" FALSE \
"Enable Outputs (Output Events)" 6 \
"Wait for DCI Match (Output Events)" NoWait
"Wait for DCI Match (Output Events)" NoWait
SIM_MODEL_PROPERTIES = ""