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rfnoc: Add Split Stream RFNoC block

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Original-commit: c27c8db011ea6ad1d0682ee06eede75989622b95
This commit is contained in:
Wade Fife
2020-05-28 14:49:32 -05:00
committed by Aaron Rossetto
parent d3615aefe0
commit 6a5a23a7a2
6 changed files with 932 additions and 0 deletions
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lib/rfnoc/blocks/rfnoc_block_split_stream/Makefile
+44
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#
# Copyright 2020 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
#-------------------------------------------------
# Top-of-Makefile
#-------------------------------------------------
# Define BASE_DIR to point to the "top" dir
BASE_DIR = $(abspath ../../../../top)
# Include viv_sim_preample after defining BASE_DIR
include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
#-------------------------------------------------
# Design Specific
#-------------------------------------------------
# Include makefiles and sources for the DUT and its
# dependencies.
include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs
include $(BASE_DIR)/../lib/rfnoc/utils/Makefile.srcs
include Makefile.srcs
DESIGN_SRCS += $(abspath \
$(RFNOC_CORE_SRCS) \
$(RFNOC_UTIL_SRCS) \
$(RFNOC_OOT_SRCS) \
)
#-------------------------------------------------
# Testbench Specific
#-------------------------------------------------
SIM_TOP = rfnoc_block_split_stream_all_tb
SIM_SRCS = \
$(abspath rfnoc_block_split_stream_tb.sv) \
$(abspath rfnoc_block_split_stream_all_tb.sv) \
#-------------------------------------------------
# Bottom-of-Makefile
#-------------------------------------------------
# Include all simulator specific makefiles here
# Each should define a unique target to simulate
# e.g. xsim, vsim, etc and a common "clean" target
include $(BASE_DIR)/../tools/make/viv_simulator.mak