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fpga: removed superfluous B2x0 files

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Original-commit: 09882ad86432db5087f85764c02989dbfc70fd3f
This commit is contained in:
Nicholas Corgan
2014-02-20 06:05:38 -08:00
parent fbbc991a7d
commit 65d3d1eabd
43 changed files with 0 additions and 112988 deletions
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top/b200/planahead/planahead.data/runs/impl_1/constrs_in.xml
-25
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@@ -1,25 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<DARoots Version="1" Minor="26">
<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<File Path="$PSRCDIR/constrs_1/imports/b200/b200.ucf">
<FileInfo>
<Attr Name="ImportPath" Val="$PPRDIR/../b200.ucf"/>
<Attr Name="ImportTime" Val="1358988004"/>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInImplementation" Val="1"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/constrs_1/imports/b200/timing.ucf">
<FileInfo>
<Attr Name="ImportPath" Val="$PPRDIR/../timing.ucf"/>
<Attr Name="ImportTime" Val="1359506480"/>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInImplementation" Val="1"/>
</FileInfo>
</File>
<Config>
<Option Name="ConstrsType" Val="UCF"/>
</Config>
</FileSet>
</DARoots>
top/b200/planahead/planahead.data/runs/impl_1/constrs_out.xml
-20
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@@ -1,20 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<DARoots Version="1" Minor="26">
<FileSet Name="constrs_out" Type="Constrs" RelSrcDir="$PRUNDIR/impl_1/.constrs">
<File Path="$PRUNDIR/impl_1/.constrs/b200.ucf">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInImplementation" Val="1"/>
</FileInfo>
</File>
<File Path="$PRUNDIR/impl_1/.constrs/timing.ucf">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInImplementation" Val="1"/>
</FileInfo>
</File>
<Config>
<Option Name="ConstrsType" Val="UCF"/>
</Config>
</FileSet>
</DARoots>
top/b200/planahead/planahead.data/runs/impl_1/impl_1.psg
-20
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@@ -1,20 +0,0 @@
<?xml version="1.0"?>
<Strategy Version="1" Minor="2">
<StratHandle Name="ISE Defaults" Flow="ISE14">
<Desc>ISE Defaults, including packing registers in IOs off</Desc>
</StratHandle>
<Step Id="ngdbuild">
</Step>
<Step Id="map">
<Option Id="FFPackEnum">3</Option>
</Step>
<Step Id="par">
</Step>
<Step Id="trce">
</Step>
<Step Id="xdl">
</Step>
<Step Id="bitgen">
</Step>
</Strategy>
top/b200/planahead/planahead.data/runs/impl_1/sources.xml
-18
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@@ -1,18 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<DARoots Version="1" Minor="26">
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/imports/build/b200.ngc">
<FileInfo>
<Attr Name="ImportPath" Val="$PPRDIR/../build/b200.ngc"/>
<Attr Name="ImportTime" Val="1359508205"/>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInImplementation" Val="1"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="b200"/>
</Config>
</FileSet>
</DARoots>