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fpga: lib: Add initial value to ram_2port

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Original-commit: da5c64bf4f631012b5969890a751084c998dd154
This commit is contained in:
Markus Schill
2025-04-09 13:50:17 -05:00
committed by Wade Fife
parent c9d2c066f3
commit 6386d90b35
2 changed files with 25 additions and 21 deletions
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lib/control/ram_2port.v
+13 -11
View File
@@ -52,12 +52,14 @@
`undef RAM_DIRECTIVE `undef RAM_DIRECTIVE
module ram_2port #( module ram_2port #(
parameter DWIDTH = 32, // Width of the memory block parameter DWIDTH = 32, // Width of the memory block
parameter AWIDTH = 9, // log2 of the depth of the memory block parameter AWIDTH = 9, // log2 of the depth of the memory block
parameter RW_MODE = "READ-FIRST", // Read-write mode {READ-FIRST, WRITE-FIRST, NO-CHANGE, B-READ-ONLY} parameter RW_MODE = "READ-FIRST", // Read-write mode {READ-FIRST, WRITE-FIRST, NO-CHANGE, B-READ-ONLY}
parameter RAM_TYPE = "AUTOMATIC", // Type of RAM to infer {AUTOMATIC, REG, LUTRAM, BRAM, URAM} parameter RAM_TYPE = "AUTOMATIC", // Type of RAM to infer {AUTOMATIC, REG, LUTRAM, BRAM, URAM}
parameter OUT_REG = 0, // Instantiate an output register? (+1 cycle of read latency) parameter OUT_REG = 0, // Instantiate an output register? (+1 cycle of read latency)
parameter INIT_FILE = "" // Optionally initialize memory with this file parameter INIT_FILE = "", // Optionally initialize memory with this file
parameter INIT_VAL = {DWIDTH{1'b0}} // Optionally initialize output registers with this value and
// memory will be filled with this value if INIT_FILE is empty
) ( ) (
input wire clka, input wire clka,
input wire ena, input wire ena,
@@ -78,7 +80,7 @@ module ram_2port #(
if (RAM_TYPE == "URAM") if (RAM_TYPE == "URAM")
ram_2port_impl_uram #( ram_2port_impl_uram #(
.DWIDTH(DWIDTH), .AWIDTH(AWIDTH), .RW_MODE(RW_MODE), .DWIDTH(DWIDTH), .AWIDTH(AWIDTH), .RW_MODE(RW_MODE),
.OUT_REG(OUT_REG), .INIT_FILE(INIT_FILE) .OUT_REG(OUT_REG), .INIT_FILE(INIT_FILE), .INIT_VAL(INIT_VAL)
) impl ( ) impl (
.clka(clka), .ena(ena), .wea(wea), .addra(addra), .dia(dia), .doa(doa), .clka(clka), .ena(ena), .wea(wea), .addra(addra), .dia(dia), .doa(doa),
.clkb(clkb), .enb(enb), .web(web), .addrb(addrb), .dib(dib), .dob(dob) .clkb(clkb), .enb(enb), .web(web), .addrb(addrb), .dib(dib), .dob(dob)
@@ -86,7 +88,7 @@ module ram_2port #(
else if (RAM_TYPE == "BRAM") else if (RAM_TYPE == "BRAM")
ram_2port_impl_bram #( ram_2port_impl_bram #(
.DWIDTH(DWIDTH), .AWIDTH(AWIDTH), .RW_MODE(RW_MODE), .DWIDTH(DWIDTH), .AWIDTH(AWIDTH), .RW_MODE(RW_MODE),
.OUT_REG(OUT_REG), .INIT_FILE(INIT_FILE) .OUT_REG(OUT_REG), .INIT_FILE(INIT_FILE), .INIT_VAL(INIT_VAL)
) impl ( ) impl (
.clka(clka), .ena(ena), .wea(wea), .addra(addra), .dia(dia), .doa(doa), .clka(clka), .ena(ena), .wea(wea), .addra(addra), .dia(dia), .doa(doa),
.clkb(clkb), .enb(enb), .web(web), .addrb(addrb), .dib(dib), .dob(dob) .clkb(clkb), .enb(enb), .web(web), .addrb(addrb), .dib(dib), .dob(dob)
@@ -94,7 +96,7 @@ module ram_2port #(
else if (RAM_TYPE == "LUTRAM") else if (RAM_TYPE == "LUTRAM")
ram_2port_impl_lutram #( ram_2port_impl_lutram #(
.DWIDTH(DWIDTH), .AWIDTH(AWIDTH), .RW_MODE(RW_MODE), .DWIDTH(DWIDTH), .AWIDTH(AWIDTH), .RW_MODE(RW_MODE),
.OUT_REG(OUT_REG), .INIT_FILE(INIT_FILE) .OUT_REG(OUT_REG), .INIT_FILE(INIT_FILE), .INIT_VAL(INIT_VAL)
) impl ( ) impl (
.clka(clka), .ena(ena), .wea(wea), .addra(addra), .dia(dia), .doa(doa), .clka(clka), .ena(ena), .wea(wea), .addra(addra), .dia(dia), .doa(doa),
.clkb(clkb), .enb(enb), .web(web), .addrb(addrb), .dib(dib), .dob(dob) .clkb(clkb), .enb(enb), .web(web), .addrb(addrb), .dib(dib), .dob(dob)
@@ -102,7 +104,7 @@ module ram_2port #(
else if (RAM_TYPE == "REG") else if (RAM_TYPE == "REG")
ram_2port_impl_reg #( ram_2port_impl_reg #(
.DWIDTH(DWIDTH), .AWIDTH(AWIDTH), .RW_MODE(RW_MODE), .DWIDTH(DWIDTH), .AWIDTH(AWIDTH), .RW_MODE(RW_MODE),
.OUT_REG(OUT_REG), .INIT_FILE(INIT_FILE) .OUT_REG(OUT_REG), .INIT_FILE(INIT_FILE), .INIT_VAL(INIT_VAL)
) impl ( ) impl (
.clka(clka), .ena(ena), .wea(wea), .addra(addra), .dia(dia), .doa(doa), .clka(clka), .ena(ena), .wea(wea), .addra(addra), .dia(dia), .doa(doa),
.clkb(clkb), .enb(enb), .web(web), .addrb(addrb), .dib(dib), .dob(dob) .clkb(clkb), .enb(enb), .web(web), .addrb(addrb), .dib(dib), .dob(dob)
@@ -110,7 +112,7 @@ module ram_2port #(
else else
ram_2port_impl_auto #( ram_2port_impl_auto #(
.DWIDTH(DWIDTH), .AWIDTH(AWIDTH), .RW_MODE(RW_MODE), .DWIDTH(DWIDTH), .AWIDTH(AWIDTH), .RW_MODE(RW_MODE),
.OUT_REG(OUT_REG), .INIT_FILE(INIT_FILE) .OUT_REG(OUT_REG), .INIT_FILE(INIT_FILE), .INIT_VAL(INIT_VAL)
) impl ( ) impl (
.clka(clka), .ena(ena), .wea(wea), .addra(addra), .dia(dia), .doa(doa), .clka(clka), .ena(ena), .wea(wea), .addra(addra), .dia(dia), .doa(doa),
.clkb(clkb), .enb(enb), .web(web), .addrb(addrb), .dib(dib), .dob(dob) .clkb(clkb), .enb(enb), .web(web), .addrb(addrb), .dib(dib), .dob(dob)
lib/control/ram_2port_impl.vh
+10 -8
View File
@@ -8,11 +8,13 @@
// Requires `RAM_MOD_NAME and `RAM_DIRECTIVE to be defined // Requires `RAM_MOD_NAME and `RAM_DIRECTIVE to be defined
module `RAM_MOD_NAME #( module `RAM_MOD_NAME #(
parameter DWIDTH = 32, // Width of the memory block parameter DWIDTH = 32, // Width of the memory block
parameter AWIDTH = 9, // log2 of the depth of the memory block parameter AWIDTH = 9, // log2 of the depth of the memory block
parameter RW_MODE = "READ-FIRST", // Read-write mode {READ-FIRST, WRITE-FIRST, NO-CHANGE, B-READ-ONLY} parameter RW_MODE = "READ-FIRST", // Read-write mode {READ-FIRST, WRITE-FIRST, NO-CHANGE, B-READ-ONLY}
parameter OUT_REG = 0, // Instantiate an output register? (+1 cycle of read latency) parameter OUT_REG = 0, // Instantiate an output register? (+1 cycle of read latency)
parameter INIT_FILE = "" // Optionally initialize memory with this file parameter INIT_FILE = "", // Optionally initialize memory with this file
parameter INIT_VAL = {DWIDTH{1'b0}} // Optionally initialize output registers with this value and
// memory will be filled with this value if INIT_FILE is empty
) ( ) (
input wire clka, input wire clka,
input wire ena, input wire ena,
@@ -40,15 +42,15 @@ module `RAM_MOD_NAME #(
integer i; integer i;
initial begin initial begin
for (i = 0; i < (1<<AWIDTH); i = i + 1) begin for (i = 0; i < (1<<AWIDTH); i = i + 1) begin
ram[i] = {DWIDTH{1'b0}}; ram[i] = INIT_VAL;
end end
end end
end endgenerate end endgenerate
reg [DWIDTH-1:0] doa_r = 'h0, dob_r = 'h0; reg [DWIDTH-1:0] doa_r = INIT_VAL, dob_r = INIT_VAL;
generate if (OUT_REG == 1) begin generate if (OUT_REG == 1) begin
// A 2 clock cycle read latency with improve clock-to-out timing // A 2 clock cycle read latency with improve clock-to-out timing
reg [DWIDTH-1:0] doa_rr = 'h0, dob_rr = 'h0; reg [DWIDTH-1:0] doa_rr = INIT_VAL, dob_rr = INIT_VAL;
always @(posedge clka) always @(posedge clka)
if (ena) begin if (ena) begin