fpga: x300: Upgrade to Vivado 2021.1

Original-commit: 629cee33d919ef8a0b742790f5fcc642b392abcd
2022-08-25 13:55:30 -05:00
parent 2997319b47
commit 6193c765fe
18 changed files with 738 additions and 274 deletions
@@ -63,8 +63,8 @@ $(VIVADO_PATH)/data/verilog/src/glbl.v \
 ))

 MODELSIM_LIBS += \
-fifo_generator_v13_2_4 \
-blk_mem_gen_v8_4_3 \
+fifo_generator_v13_2_5 \
+blk_mem_gen_v8_4_4 \

 modelsim vlint : SIM_SRCS += $(MODELSIM_IP_SRCS)