diff --git a/top/x300/ip/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.xci b/top/x300/ip/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.xci
index 0bfdcb8..27b57f8 100644
--- a/top/x300/ip/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.xci
+++ b/top/x300/ip/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.xci
@@ -32,7 +32,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -63,7 +63,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -94,7 +94,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -125,7 +125,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -156,7 +156,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -187,7 +187,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -218,7 +218,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -249,7 +249,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -280,7 +280,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -311,7 +311,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -342,7 +342,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -373,7 +373,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -404,7 +404,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -435,7 +435,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -466,7 +466,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -497,7 +497,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -517,337 +517,394 @@
100000000
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
+ 0
0
- 0.000
+ 0.0
+ 0
0
- 0.000
+ 0.0
+ 0
0
- 0.000
+ 0.0
+ 0
0
- 0.000
+ 0.0
+ 0
0
- 0.000
+ 0.0
0
0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
+ 0
0
- 0.000
+ 0.0
false
100000000
0
@@ -859,7 +916,7 @@
0
0
undef
- 0.000
+ 0.0
0
0
0
@@ -868,110 +925,131 @@
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
0
0
0
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
@@ -983,90 +1061,108 @@
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
0
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
undef
undef
+ undef
undef
undef
undef
@@ -1076,8 +1172,9 @@
100000000
+ 0
0
- 0.000
+ 0.0
0
0
@@ -1088,7 +1185,7 @@
0
0
undef
- 0.000
+ 0.0
0
0
0
@@ -1101,24 +1198,29 @@
0
0
undef
- 0.000
+ 0.0
0
0
0
0
100000000
+ 0
0
- 0.000
- 156.25
+ 0.0
+
+ 156250000
undef
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
+ 0
0
- 0.000
+ 0.0
100000000
0
@@ -1127,7 +1229,7 @@
0
0
undef
- 0.000
+ 0.0
8
0
0
@@ -1140,7 +1242,7 @@
0
0
undef
- 0.000
+ 0.0
8
0
0
@@ -1153,7 +1255,7 @@
0
0
undef
- 0.000
+ 0.0
0
0
0
@@ -1166,7 +1268,7 @@
0
0
undef
- 0.000
+ 0.0
0
0
0
@@ -1418,12 +1520,12 @@
TRUE
TRUE
IP_Flow
- 0
+ 6
TRUE
.
.
- 2019.1
+ 2021.1
OUT_OF_CONTEXT
@@ -1773,6 +1875,56 @@
+
+
+
diff --git a/top/x300/ip/axi4_dualport_sram/axi4_dualport_sram.xci b/top/x300/ip/axi4_dualport_sram/axi4_dualport_sram.xci
index f06d744..b1c55a7 100644
--- a/top/x300/ip/axi4_dualport_sram/axi4_dualport_sram.xci
+++ b/top/x300/ip/axi4_dualport_sram/axi4_dualport_sram.xci
@@ -33,7 +33,7 @@
1
2
1
- 0.000
+ 0.0
AXI4
READ_WRITE
0
@@ -64,7 +64,7 @@
1
2
1
- 0.000
+ 0.0
AXI4
READ_WRITE
0
@@ -86,8 +86,9 @@
100000000
+ 0
0
- 0.000
+ 0.0
0
18
18
@@ -250,12 +251,12 @@
TRUE
TRUE
IP_Flow
- 3
+ 4
TRUE
.
.
- 2019.1
+ 2021.1
OUT_OF_CONTEXT
@@ -307,6 +308,24 @@
+
+
+
diff --git a/top/x300/ip/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci b/top/x300/ip/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci
index 3747f05..fef9e17 100644
--- a/top/x300/ip/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci
+++ b/top/x300/ip/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci
@@ -13,13 +13,15 @@
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
1
0
0
@@ -43,7 +45,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -59,7 +61,7 @@
0
0
undef
- 0.000
+ 0.0
8
0
0
@@ -68,12 +70,14 @@
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
0
1
0
@@ -98,7 +102,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -114,7 +118,7 @@
0
0
undef
- 0.000
+ 0.0
8
0
0
@@ -123,8 +127,9 @@
100000000
+ 0
0
- 0.000
+ 0.0
0
0
0
@@ -509,12 +514,12 @@
TRUE
TRUE
IP_Flow
- 4
+ 5
TRUE
.
.
- 2019.1
+ 2021.1
OUT_OF_CONTEXT
@@ -577,6 +582,22 @@
+
+
+
diff --git a/top/x300/ip/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci b/top/x300/ip/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci
index 8c3264c..e3cd2cc 100644
--- a/top/x300/ip/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci
+++ b/top/x300/ip/axi64_8k_2clk_fifo/axi64_8k_2clk_fifo.xci
@@ -13,13 +13,15 @@
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
1
0
0
@@ -43,7 +45,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -59,7 +61,7 @@
0
0
undef
- 0.000
+ 0.0
8
0
0
@@ -68,12 +70,14 @@
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
0
1
0
@@ -98,7 +102,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -114,7 +118,7 @@
0
0
undef
- 0.000
+ 0.0
8
0
0
@@ -123,8 +127,9 @@
100000000
+ 0
0
- 0.000
+ 0.0
0
0
0
@@ -509,12 +514,12 @@
TRUE
TRUE
IP_Flow
- 4
+ 5
TRUE
.
.
- 2019.1
+ 2021.1
OUT_OF_CONTEXT
@@ -575,6 +580,22 @@
+
+
+
diff --git a/top/x300/ip/bootram/bootram.xci b/top/x300/ip/bootram/bootram.xci
index ec46d7a..496cea0 100644
--- a/top/x300/ip/bootram/bootram.xci
+++ b/top/x300/ip/bootram/bootram.xci
@@ -33,7 +33,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -64,7 +64,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -86,8 +86,9 @@
100000000
+ 0
0
- 0.000
+ 0.0
0
13
13
@@ -250,12 +251,12 @@
TRUE
TRUE
IP_Flow
- 3
+ 4
TRUE
.
.
- 2019.1
+ 2021.1
OUT_OF_CONTEXT
@@ -311,6 +312,14 @@
+
+
+
diff --git a/top/x300/ip/bus_clk_gen/bus_clk_gen.xci b/top/x300/ip/bus_clk_gen/bus_clk_gen.xci
index dd1f688..e760100 100644
--- a/top/x300/ip/bus_clk_gen/bus_clk_gen.xci
+++ b/top/x300/ip/bus_clk_gen/bus_clk_gen.xci
@@ -21,58 +21,67 @@
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
1
LEVEL_HIGH
100000000
+ 0
0
- 0.000
+ 0.0
0
0
100000000
+ 0
0
- 0.000
+ 0.0
1
0
0
@@ -96,7 +105,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -122,14 +131,14 @@
100.0
0000
0000
- 187.500
+ 187.50000
0000
0000
- 125.000
+ 125.00000
BUFG
50.0
false
- 187.500
+ 187.50000
0.000
50.000
187.5
@@ -137,11 +146,11 @@
1
0000
0000
- 93.750
+ 93.75000
No_buffer
50.0
false
- 125.000
+ 125.00000
0.000
50.000
125.000
@@ -150,11 +159,11 @@
1
0000
0000
- 214.286
+ 214.28571
BUFG
50.0
false
- 93.750
+ 93.75000
0.000
50.000
93.75
@@ -167,7 +176,7 @@
BUFG
50.0
false
- 214.286
+ 214.28571
0.000
50.000
215
@@ -229,13 +238,15 @@
1
1.5
2.0
- 0.872093023255814
- 1.875
- 1.875
- 1.875
+ 0.875
+ 0.125
+ 0.125
+ 0.125
DOUT
DRDY
DWE
+ 49.000
+ 1.000
0
0
0
@@ -309,18 +320,23 @@
0.010
0.010
FALSE
+ 64.000
+ 2.000
4
+ 0
Output Output Phase Duty Cycle Pk-to-Pk Phase
Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
- CLK_OUT1___187.500______0.000______50.0_______85.263_____73.940
- CLK_OUT2_UNBUF___125.000______0.000______50.0_______91.831_____73.940
- CLK_OUT3____93.750______0.000______50.0_______96.813_____73.940
- CLK_OUT4___214.286______0.000______50.0_______83.210_____73.940
+ CLK_OUT1__187.50000______0.000______50.0_______85.263_____73.940
+ CLK_OUT2_UNBUF__125.00000______0.000______50.0_______91.831_____73.940
+ CLK_OUT3__93.75000______0.000______50.0_______96.813_____73.940
+ CLK_OUT4__214.28571______0.000______50.0_______83.210_____73.940
no_CLK_OUT5_output
no_CLK_OUT6_output
no_CLK_OUT7_output
0
0
+ 128.000
+ 1.000
WAVEFORM
UNKNOWN
false
@@ -411,6 +427,8 @@
0
0
0
+ 1866.000
+ 800.000
bus_clk_gen
MMCM
false
@@ -583,6 +601,7 @@
0.010
false
4
+ false
false
false
WAVEFORM
@@ -681,12 +700,12 @@
TRUE
TRUE
IP_Flow
- 3
+ 8
TRUE
.
.
- 2019.1
+ 2021.1
OUT_OF_CONTEXT
@@ -779,6 +798,21 @@
+
+
+
diff --git a/top/x300/ip/fifo_4k_2clk/fifo_4k_2clk.xci b/top/x300/ip/fifo_4k_2clk/fifo_4k_2clk.xci
index dddfacc..12b46ed 100644
--- a/top/x300/ip/fifo_4k_2clk/fifo_4k_2clk.xci
+++ b/top/x300/ip/fifo_4k_2clk/fifo_4k_2clk.xci
@@ -13,13 +13,15 @@
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
1
0
0
@@ -43,7 +45,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -59,7 +61,7 @@
0
0
undef
- 0.000
+ 0.0
0
0
0
@@ -68,12 +70,14 @@
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
0
1
0
@@ -98,7 +102,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -114,7 +118,7 @@
0
0
undef
- 0.000
+ 0.0
0
0
0
@@ -123,8 +127,9 @@
100000000
+ 0
0
- 0.000
+ 0.0
0
0
0
@@ -509,12 +514,12 @@
TRUE
TRUE
IP_Flow
- 4
+ 5
TRUE
.
.
- 2019.1
+ 2021.1
OUT_OF_CONTEXT
@@ -569,6 +574,14 @@
+
+
+
diff --git a/top/x300/ip/fifo_short_2clk/fifo_short_2clk.xci b/top/x300/ip/fifo_short_2clk/fifo_short_2clk.xci
index 4976145..e82417a 100644
--- a/top/x300/ip/fifo_short_2clk/fifo_short_2clk.xci
+++ b/top/x300/ip/fifo_short_2clk/fifo_short_2clk.xci
@@ -13,13 +13,15 @@
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
1
0
0
@@ -43,7 +45,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -59,7 +61,7 @@
0
0
undef
- 0.000
+ 0.0
0
0
0
@@ -68,12 +70,14 @@
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
0
1
0
@@ -98,7 +102,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -114,7 +118,7 @@
0
0
undef
- 0.000
+ 0.0
0
0
0
@@ -123,8 +127,9 @@
100000000
+ 0
0
- 0.000
+ 0.0
0
0
0
@@ -509,12 +514,12 @@
TRUE
TRUE
IP_Flow
- 4
+ 5
TRUE
.
.
- 2019.1
+ 2021.1
OUT_OF_CONTEXT
@@ -571,6 +576,14 @@
+
+
+
diff --git a/top/x300/ip/input_sample_fifo/input_sample_fifo.xci b/top/x300/ip/input_sample_fifo/input_sample_fifo.xci
index 1f3e58e..a2df0a6 100644
--- a/top/x300/ip/input_sample_fifo/input_sample_fifo.xci
+++ b/top/x300/ip/input_sample_fifo/input_sample_fifo.xci
@@ -13,13 +13,15 @@
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
1
0
0
@@ -43,7 +45,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -59,7 +61,7 @@
0
0
undef
- 0.000
+ 0.0
0
0
0
@@ -68,12 +70,14 @@
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
0
1
0
@@ -98,7 +102,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -114,7 +118,7 @@
0
0
undef
- 0.000
+ 0.0
0
0
0
@@ -123,8 +127,9 @@
100000000
+ 0
0
- 0.000
+ 0.0
0
0
0
@@ -509,12 +514,12 @@
TRUE
TRUE
IP_Flow
- 4
+ 5
TRUE
.
.
- 2019.1
+ 2021.1
OUT_OF_CONTEXT
@@ -568,6 +573,14 @@
+
+
+
diff --git a/top/x300/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci b/top/x300/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci
index 245a6dd..c0a6d61 100644
--- a/top/x300/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci
+++ b/top/x300/ip/one_gig_eth_pcs_pma/one_gig_eth_pcs_pma.xci
@@ -7,7 +7,7 @@
one_gig_eth_pcs_pma
-
+
1
1
@@ -16,51 +16,63 @@
+ 0
0
+ 0
0
+ 0
0
+ 0
0
+ 0
0
+ 0
0
+ 0
0
+ 0
0
+ 0
0
+ 0
0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
false
false
false
@@ -69,37 +81,54 @@
+ 0
0
+ 0
0
false
100000000
+ 0
0
+ 0
0
100000000
+ 0
0
- 0.000
+ 0.0
+ undef
+ undef
+ undef
+ undef
+ undef
+ undef
+ undef
+ undef
+ undef
+ undef
+ undef
+ undef
100000000
0
- 0.000
+ 0.0
100000000
0
- 0.000
+ 0.0
false
false
false
@@ -110,14 +139,16 @@
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
false
false
false
@@ -125,29 +156,35 @@
100000000
+ 0
0
- 0.000
+ 0.0
0
0
+ 0
0
+ 0
0
+ 0
0
+ 0
0
+ 0
0
ACTIVE_LOW
ACTIVE_LOW
@@ -176,7 +213,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -187,31 +224,38 @@
100000000
+ 0
0
- 0.000
+ 0.0
0
+ 0
0
+ 0
0
+ 0
0
+ 0
0
+ 0
0
true
0
+ 0
0
false
false
@@ -221,7 +265,7 @@
DIFF_PAIR_0
DIFF_PAIR_1
kintex7
- 0
+ Sync
one_gig_eth_pcs_pma
50
false
@@ -314,12 +358,12 @@
TRUE
TRUE
IP_Flow
- 6
+ 4
TRUE
.
.
- 2019.1
+ 2021.1
OUT_OF_CONTEXT
@@ -346,6 +390,31 @@
+
+
+
diff --git a/top/x300/ip/pcie_clk_gen/pcie_clk_gen.xci b/top/x300/ip/pcie_clk_gen/pcie_clk_gen.xci
index a360356..bc3f486 100644
--- a/top/x300/ip/pcie_clk_gen/pcie_clk_gen.xci
+++ b/top/x300/ip/pcie_clk_gen/pcie_clk_gen.xci
@@ -21,34 +21,39 @@
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
1
LEVEL_HIGH
100000000
+ 0
0
- 0.000
+ 0.0
0
0
100000000
+ 0
0
- 0.000
+ 0.0
1
0
0
@@ -72,7 +77,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -98,14 +103,14 @@
100.0
0000
0000
- 40.000
+ 40.00000
0000
0000
- 200.000
+ 200.00000
BUFH
50.0
false
- 40.000
+ 40.00000
0.000
50.000
40
@@ -117,7 +122,7 @@
BUFH
50.0
false
- 200.000
+ 200.00000
0.000
50.000
200
@@ -204,14 +209,16 @@
0000
1
0.2
- 0.4
- 0.4
- 0.4
- 0.4
- 0.4
+ 0.04
+ 0.04
+ 0.04
+ 0.04
+ 0.04
DOUT
DRDY
DWE
+ 49.000
+ 1.000
0
0
0
@@ -285,11 +292,14 @@
0.100
0.010
FALSE
+ 64.000
+ 2.000
2
+ 0
Output Output Phase Duty Cycle Pk-to-Pk Phase
Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
- CLK_OUT1____40.000______0.000______50.0______353.417_____96.948
- CLK_OUT2___200.000______0.000______50.0______192.299_____96.948
+ CLK_OUT1__40.00000______0.000______50.0______353.417_____96.948
+ CLK_OUT2__200.00000______0.000______50.0______192.299_____96.948
no_CLK_OUT3_output
no_CLK_OUT4_output
no_CLK_OUT5_output
@@ -297,6 +307,8 @@
no_CLK_OUT7_output
0
0
+ 128.000
+ 1.000
WAVEFORM
UNKNOWN
false
@@ -387,6 +399,8 @@
0
0
0
+ 1866.000
+ 800.000
pcie_clk_gen
MMCM
false
@@ -559,6 +573,7 @@
0.010
false
2
+ false
false
false
WAVEFORM
@@ -657,12 +672,12 @@
TRUE
TRUE
IP_Flow
- 3
+ 8
TRUE
.
.
- 2019.1
+ 2021.1
OUT_OF_CONTEXT
@@ -745,6 +760,15 @@
+
+
+
diff --git a/top/x300/ip/radio_clk_gen/radio_clk_gen.xci b/top/x300/ip/radio_clk_gen/radio_clk_gen.xci
index 9c68fce..5fad9f0 100644
--- a/top/x300/ip/radio_clk_gen/radio_clk_gen.xci
+++ b/top/x300/ip/radio_clk_gen/radio_clk_gen.xci
@@ -21,34 +21,39 @@
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
1
LEVEL_HIGH
100000000
+ 0
0
- 0.000
+ 0.0
0
0
100000000
+ 0
0
- 0.000
+ 0.0
1
0
0
@@ -72,7 +77,7 @@
1
1
1
- 0.000
+ 0.0
AXI4LITE
READ_WRITE
0
@@ -98,14 +103,14 @@
100.0
0000
0000
- 200.000
+ 200.00000
0000
0000
- 400.000
+ 400.00000
BUFG
50.0
false
- 200.000
+ 200.00000
0.000
50.000
200.000
@@ -113,11 +118,11 @@
1
0000
0000
- 400.000
+ 400.00000
BUFG
50.0
false
- 400.000
+ 400.00000
-45.000
50.000
400.000
@@ -130,7 +135,7 @@
BUFG
50.0
false
- 400.000
+ 400.00000
60.000
50.000
400.000
@@ -205,13 +210,15 @@
1
0.5
0.5
- 2.0
- 2.0
- 2.0
- 2.0
+ 0.16666666666666666
+ 0.16666666666666666
+ 0.16666666666666666
+ 0.16666666666666666
DOUT
DRDY
DWE
+ 93.000
+ 1.000
0
0
0
@@ -285,18 +292,23 @@
0.010
0.010
FALSE
+ 64.000
+ 2.000
3
+ 0
Output Output Phase Duty Cycle Pk-to-Pk Phase
Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
- CLK_OUT1___200.000______0.000______50.0_______92.799_____82.655
- CLK_OUT2___400.000____-45.000______50.0_______81.254_____82.655
- CLK_OUT3___400.000_____60.000______50.0_______81.254_____82.655
+ CLK_OUT1__200.00000______0.000______50.0_______92.799_____82.655
+ CLK_OUT2__400.00000____-45.000______50.0_______81.254_____82.655
+ CLK_OUT3__400.00000_____60.000______50.0_______81.254_____82.655
no_CLK_OUT4_output
no_CLK_OUT5_output
no_CLK_OUT6_output
no_CLK_OUT7_output
0
0
+ 128.000
+ 1.000
WAVEFORM
UNKNOWN
false
@@ -387,6 +399,8 @@
0
0
0
+ 1440.000
+ 600.000
radio_clk_gen
MMCM
false
@@ -559,6 +573,7 @@
0.010
false
3
+ false
false
false
WAVEFORM
@@ -657,12 +672,12 @@
TRUE
TRUE
IP_Flow
- 3
+ 8
TRUE
.
.
- 2019.1
+ 2021.1
OUT_OF_CONTEXT
@@ -748,6 +763,16 @@
+
+
+
diff --git a/top/x300/ip/radio_clk_gen/radio_clk_gen.xdc.patch b/top/x300/ip/radio_clk_gen/radio_clk_gen.xdc.patch
index d4a0c07..af54aa9 100644
--- a/top/x300/ip/radio_clk_gen/radio_clk_gen.xdc.patch
+++ b/top/x300/ip/radio_clk_gen/radio_clk_gen.xdc.patch
@@ -1,4 +1,4 @@
56,58d55
< create_clock -period 5.000 [get_ports clk_in1_p]
-< set_input_jitter [get_clocks -of_objects [get_ports clk_in1_p]] 0.05
+< set_input_jitter [get_clocks -of_objects [get_ports clk_in1_p]] 0.050
<
diff --git a/top/x300/ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci b/top/x300/ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci
index 453f49c..9f04c6f 100644
--- a/top/x300/ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci
+++ b/top/x300/ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci
@@ -16,18 +16,21 @@
0
+ 0
0
- 0.000
+ 0.0
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
0
0
0
@@ -37,14 +40,16 @@
100000000
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
0
false
0
@@ -53,83 +58,98 @@
100000000
+ 0
0
- 0.000
+ 0.0
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
+ 0
0
- 0.000
+ 0.0
100000000
+ 0
0
- 0.000
+ 0.0
+ 0
0
- 0.000
+ 0.0
false
0
0
+ 0
0
- 0.000
+ 0.0
0
+ 0
0
- 0.000
+ 0.0
+ 0
0
- 0.000
+ 0.0
0
+ 0
0
- 0.000
+ 0.0
+ 0
0
- 0.000
+ 0.0
+ 0
0
- 0.000
+ 0.0
+ 0
0
- 0.000
+ 0.0
0
ten_gig_eth_pcs_pma
100.00
@@ -179,14 +199,45 @@
TRUE
TRUE
IP_Flow
- 15
+ 19
TRUE
.
.
- 2019.1
+ 2021.1
OUT_OF_CONTEXT
+
+
+
+
+
+
+
diff --git a/top/x300/setupenv.sh b/top/x300/setupenv.sh
index 6065a5c..5553a44 100644
--- a/top/x300/setupenv.sh
+++ b/top/x300/setupenv.sh
@@ -1,6 +1,6 @@
#!/bin/bash
-VIVADO_VER=2019.1
+VIVADO_VER=2021.1
DISPLAY_NAME="USRP-X3x0"
REPO_BASE_PATH=$(cd "$(dirname "${BASH_SOURCE[0]}")/../.." && pwd)
diff --git a/top/x300/sim/aurora_loopback/Makefile b/top/x300/sim/aurora_loopback/Makefile
index b7621c4..c4dc4a3 100644
--- a/top/x300/sim/aurora_loopback/Makefile
+++ b/top/x300/sim/aurora_loopback/Makefile
@@ -69,7 +69,7 @@ MODELSIM_LIBS += \
unisims_ver \
unimacro_ver \
secureip \
-fifo_generator_v13_2_4 \
+fifo_generator_v13_2_5 \
MODELSIM_ARGS += glbl -t 1fs
diff --git a/top/x300/sim/dram_fifo/Makefile b/top/x300/sim/dram_fifo/Makefile
index 6273c60..f790a3b 100644
--- a/top/x300/sim/dram_fifo/Makefile
+++ b/top/x300/sim/dram_fifo/Makefile
@@ -68,13 +68,13 @@ $(VIVADO_PATH)/data/verilog/src/glbl.v \
MODELSIM_LIBS += \
secureip \
-fifo_generator_v13_2_4 \
-axi_register_slice_v2_1_19 \
+fifo_generator_v13_2_5 \
+axi_register_slice_v2_1_24 \
axi_infrastructure_v1_1_0 \
-axi_dwidth_converter_v2_1_19 \
-axi_crossbar_v2_1_20 \
-blk_mem_gen_v8_4_3 \
-axi_data_fifo_v2_1_18 \
+axi_dwidth_converter_v2_1_24 \
+axi_crossbar_v2_1_25 \
+blk_mem_gen_v8_4_4 \
+axi_data_fifo_v2_1_23 \
generic_baseblocks_v2_1_0 \
modelsim vlint : SIM_SRCS += $(MODELSIM_IP_SRCS)
diff --git a/top/x300/sim/dram_fifo_bist/Makefile b/top/x300/sim/dram_fifo_bist/Makefile
index 6a57a55..68fdfc3 100644
--- a/top/x300/sim/dram_fifo_bist/Makefile
+++ b/top/x300/sim/dram_fifo_bist/Makefile
@@ -63,8 +63,8 @@ $(VIVADO_PATH)/data/verilog/src/glbl.v \
))
MODELSIM_LIBS += \
-fifo_generator_v13_2_4 \
-blk_mem_gen_v8_4_3 \
+fifo_generator_v13_2_5 \
+blk_mem_gen_v8_4_4 \
modelsim vlint : SIM_SRCS += $(MODELSIM_IP_SRCS)