miegl/b210-k7-fpga
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

fpga: x300: Upgrade to Vivado 2021.1

Browse Source 
Original-commit: 629cee33d919ef8a0b742790f5fcc642b392abcd
This commit is contained in:
Sam O'Brien
2022-08-25 13:55:30 -05:00
committed by skooNI
parent 2997319b47
commit 6193c765fe
18 changed files with 738 additions and 274 deletions
Download Patch File Download Diff File Expand all files Collapse all files
top/x300/sim/dram_fifo/Makefile
+6 -6
View File
@@ -68,13 +68,13 @@ $(VIVADO_PATH)/data/verilog/src/glbl.v \
MODELSIM_LIBS += \
secureip \
fifo_generator_v13_2_4 \
axi_register_slice_v2_1_19 \
fifo_generator_v13_2_5 \
axi_register_slice_v2_1_24 \
axi_infrastructure_v1_1_0 \
axi_dwidth_converter_v2_1_19 \
axi_crossbar_v2_1_20 \
blk_mem_gen_v8_4_3 \
axi_data_fifo_v2_1_18 \
axi_dwidth_converter_v2_1_24 \
axi_crossbar_v2_1_25 \
blk_mem_gen_v8_4_4 \
axi_data_fifo_v2_1_23 \
generic_baseblocks_v2_1_0 \
modelsim vlint : SIM_SRCS += $(MODELSIM_IP_SRCS)