fpga: x400: Add support for X410 motherboard FPGA
Co-authored-by: Andrew Moch <Andrew.Moch@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Michael Auchter <michael.auchter@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Hector Rubio <hrubio@ni.com> Original-commit: 6d3765605262016a80f71e36357f749ea35cbe5a
This commit is contained in:
Wade Fife
committed by
Aaron Rossetto
Aaron Rossetto
co-authored by
Andrew Moch
Daniel Jepson
Javier Valenzuela
Joerg Hofrichter
Kumaran Subramoniam
Max Köhler
Michael Auchter
Paul Butler
Hector Rubio
Andrew Moch
Daniel Jepson
Javier Valenzuela
Joerg Hofrichter
Kumaran Subramoniam
Max Köhler
Michael Auchter
Paul Butler
Hector Rubio
parent
bfef20ea45
commit
61782b02d7
@@ -0,0 +1,566 @@
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//
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// Copyright 2021 Ettus Research, A National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: x4xx_qsfp_wrapper
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//
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// Description:
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//
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// Consolidates the logic necessary for a QSFP port, depending on the
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// requested protocol.
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//
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// Parameters:
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//
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// PROTOCOL : Indicates the protocol to use for each of the 4 QSFP
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// lanes. See x4xx_mgt_types.vh for possible values.
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// CPU_W : Width of CPU interface
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// CHDR_W : CHDR bus width
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// BYTE_MTU : Transport MTU in bytes
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// PORTNUM : Port number to distinguish multiple QSFP ports
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// RFNOC_PROTOVER : RFNoC protocol version for IPv4 interface
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//
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`include "./x4xx_mgt_types.vh"
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module x4xx_qsfp_wrapper #(
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// Must be a value defined in x4xx_mgt_types.vh
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parameter integer PROTOCOL [3:0] = {`MGT_Disabled,
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`MGT_Disabled,
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`MGT_Disabled,
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`MGT_Disabled},
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parameter CPU_W = 64,
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parameter CHDR_W = 64,
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parameter BYTE_MTU = $clog2(8*1024),
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parameter [ 7:0] PORTNUM = 8'd0,
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parameter [15:0] RFNOC_PROTOVER = {8'd1, 8'd0}
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)(
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// Resets
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input logic areset,
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input logic bus_rst,
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input logic clk40_rst,
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// Clocks
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input logic refclk_p,
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input logic refclk_n,
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input logic clk100,
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input logic bus_clk,
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// AXI-Lite register access
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AxiLiteIf.slave s_axi,
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// Ethernet DMA AXI to PS memory
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AxiIf.master axi_hp,
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// MGT high-speed IO
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output logic [3:0] tx_p,
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output logic [3:0] tx_n,
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input logic [3:0] rx_p,
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input logic [3:0] rx_n,
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// CHDR router interface
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AxiStreamIf.master e2v [4],
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AxiStreamIf.slave v2e [4],
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// ETH DMA IRQs
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output logic [3:0] eth_rx_irq,
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output logic [3:0] eth_tx_irq,
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// Misc.
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output logic rx_rec_clk_out,
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input logic [15:0] device_id,
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output logic [3:0][31:0] port_info,
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output logic [3:0] link_up,
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output logic [3:0] activity
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);
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import PkgAxiLite::*;
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localparam REG_BASE_SFP_IO = 14'h0;
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localparam REG_BASE_ETH_SWITCH = 14'h1000;
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localparam CPU_USER_W = $clog2(CPU_W/8)+1;
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localparam CHDR_USER_W = $clog2(CHDR_W/8);
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localparam REG_DWIDTH = 32;
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localparam REG_AWIDTH_MISC = 14;
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localparam logic [3:0] DISABLED = { PROTOCOL[3] == `MGT_Disabled,
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PROTOCOL[2] == `MGT_Disabled,
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PROTOCOL[1] == `MGT_Disabled,
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PROTOCOL[0] == `MGT_Disabled };
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localparam logic [3:0] IS10GBE = { PROTOCOL[3] == `MGT_10GbE,
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PROTOCOL[2] == `MGT_10GbE,
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PROTOCOL[1] == `MGT_10GbE,
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PROTOCOL[0] == `MGT_10GbE };
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localparam logic [3:0] IS100GBE = { 3'b0,PROTOCOL[0] == `MGT_100GbE };
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localparam logic [3:0] ISAURORA = { 3'b0,PROTOCOL[0] == `MGT_Aurora };
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`include "../../lib/axi4_sv/axi.vh"
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`include "../../lib/axi4lite_sv/axi_lite.vh"
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//---------------------------------------------------------------------------
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// Interfaces
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//---------------------------------------------------------------------------
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// AXI-Lite interface
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AxiLiteIf #(REG_DWIDTH,40)
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m_axi_dma[3:0] (s_axi.clk, s_axi.rst);
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// 0x0000-0x3FFF - Bottom goes to XGE top goes to UIO
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AxiLiteIf #(REG_DWIDTH,40)
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m_axi_misc[3:0] (s_axi.clk, s_axi.rst);
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AxiLiteIf_v #(REG_DWIDTH,REG_AWIDTH_MISC)
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m_axi_misc_v[3:0] (s_axi.clk, s_axi.rst);
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// 0x4000-0x5FFF - Goes to 100G Mac
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AxiLiteIf #(REG_DWIDTH,40)
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m_axi_mac[3:0] (s_axi.clk, s_axi.rst);
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// AXI (Full) for DMA back to CPU memory
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AxiIf #(128,49)
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axi_hp_dma[3:0] (s_axi.clk, s_axi.rst);
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//---------------------------------------------------------------------------
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// AXI Interconnect
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//---------------------------------------------------------------------------
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//
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// Break the incoming register request into 12 different spaces:
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//
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// 0x0_0000 - dma0
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// 0x0_8000 - misc0 - +0x0000 NIXGE
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// +0x2000 UIO
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// 0x0_C000 - mac0
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//
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// 0x1_0000 - dma1
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// 0x1_8000 - misc1 - +0x0000 NIXGE
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// +0x2000 UIO
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// 0x1_C000 - mac1
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//
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// 0x2_0000 - dma2
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// 0x2_8000 - misc2 - +0x0000 NIXGE
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// +0x2000 UIO
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// 0x2_C000 - mac2
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//
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// 0x3_0000 - dma3
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// 0x3_8000 - misc3 - +0x0000 NIXGE
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// +0x2000 UIO
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// 0x3_C000 - mac3
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//
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//---------------------------------------------------------------------------
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axi_interconnect_eth axi_interconnect_eth_i (
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.s_axi_eth (s_axi),
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.m_axi_dma (m_axi_dma),
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.m_axi_misc (m_axi_misc),
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.m_axi_mac (m_axi_mac)
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);
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//---------------------------------------------------------------------------
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// Map DMA Engine Masters to CPU Memory Port
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//---------------------------------------------------------------------------
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// Everything Disabled
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if (DISABLED == 4'b1111) begin : axi_hp_noconnect
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always_comb begin
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axi_hp.drive_read_idle();
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axi_hp.drive_aw_idle();
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axi_hp.drive_w_idle();
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axi_hp.bready = 1'b0;
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axi_hp.rready = 1'b0;
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end
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end : axi_hp_noconnect else
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// Only port0 Enabled
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if (DISABLED == 4'b1110) begin : axi_hp_directconnect
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always_comb begin
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`AXI4_ASSIGN(axi_hp,axi_hp_dma[0])
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axi_hp_dma[1].wready = 1'b0;
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axi_hp_dma[2].wready = 1'b0;
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axi_hp_dma[3].wready = 1'b0;
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axi_hp_dma[1].awready = 1'b0;
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axi_hp_dma[2].awready = 1'b0;
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axi_hp_dma[3].awready = 1'b0;
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axi_hp_dma[1].arready = 1'b0;
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axi_hp_dma[2].arready = 1'b0;
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axi_hp_dma[3].arready = 1'b0;
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axi_hp_dma[1].bvalid = 1'b0;
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axi_hp_dma[2].bvalid = 1'b0;
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axi_hp_dma[3].bvalid = 1'b0;
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axi_hp_dma[1].rvalid = 1'b0;
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axi_hp_dma[2].rvalid = 1'b0;
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axi_hp_dma[3].rvalid = 1'b0;
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end
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// All other cases
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end : axi_hp_directconnect else begin : axi_hp_interconnect
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axi_interconnect_dma axi_interconnect_dma_i (
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.m_axi_hp (axi_hp),
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.s_axi_hp_dma (axi_hp_dma)
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);
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end : axi_hp_interconnect
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//---------------------------------------------------------------------------
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// 10 Gigabit Ethernet
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//---------------------------------------------------------------------------
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logic refclk; // 156 Mhz Ref 10 GbE
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logic [0:0] qpll0_reset;
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logic [3:0] qpll0_reset_i;
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logic [0:0] qpll0_lock;
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logic [0:0] qpll0_clk;
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logic [0:0] qpll0_refclk;
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logic [0:0] qpll1_reset;
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logic [3:0] qpll1_reset_i;
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logic [0:0] qpll1_lock;
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logic [0:0] qpll1_clk;
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logic [0:0] qpll1_refclk;
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assign qpll0_reset[0] = qpll0_reset_i[0] || qpll0_reset_i[1] ||
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qpll0_reset_i[2] || qpll0_reset_i[3];
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assign qpll1_reset[0] = qpll1_reset_i[0] || qpll1_reset_i[1] ||
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qpll1_reset_i[2] || qpll1_reset_i[3];
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// The following logic is shared amongst potentially 4X10GBE interfaces
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if (IS10GBE != 0) begin : xge_common
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// Clocking signals for MGTs
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IBUFDS_GTE4 ibufds_gte4_refclk (
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.I (refclk_p),
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.IB (refclk_n),
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.CEB (1'b0),
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.O (refclk),
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.ODIV2 ()
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);
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xge_pcs_pma_common_wrapper xge_pcs_pma_common_wrapper_i (
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.refclk (refclk),
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.qpll0reset (qpll0_reset),
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.qpll0lock (qpll0_lock),
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.qpll0outclk (qpll0_clk),
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.qpll0outrefclk (qpll0_refclk),
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.qpll1reset (qpll1_reset),
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.qpll1lock (qpll1_lock),
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.qpll1outclk (qpll1_clk),
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.qpll1outrefclk (qpll1_refclk)
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);
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end : xge_common
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//---------------------------------------------------------------------------
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// Generate QSFP Lanes
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//---------------------------------------------------------------------------
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logic [3:0] rx_rec_clk_out_i;
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assign rx_rec_clk_out = rx_rec_clk_out_i[0];
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generate
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genvar lane;
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begin : mgt_lanes
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// Repeat logic for up to 4 QSFP lanes
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for(lane = 0; lane < 4; lane++) begin : lane_loop
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//---------------------------------------
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// AXI-Lite to RegPort Bridge
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//---------------------------------------
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// Map to 0x4000 space
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always_comb begin
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`AXI4LITE_ASSIGN(m_axi_misc_v[lane],m_axi_misc[lane])
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m_axi_misc_v[lane].araddr = 0;
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m_axi_misc_v[lane].araddr[13:0] = m_axi_misc[lane].araddr[13:0];
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m_axi_misc_v[lane].awaddr = 0;
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m_axi_misc_v[lane].awaddr[13:0] = m_axi_misc[lane].awaddr[13:0];
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end
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// AXI4-Lite to RegPort (PS to PL Register Access)
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// NOTE: We always have a register interface even if the block is
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// unused, so that the driver can query the status.
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typedef logic [REG_AWIDTH_MISC-1:0] reg_addr_t;
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typedef logic [REG_DWIDTH-1:0] reg_data_t;
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logic reg_wr_req;
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reg_addr_t reg_wr_addr;
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reg_data_t reg_wr_data;
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logic reg_rd_req;
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reg_addr_t reg_rd_addr;
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logic reg_rd_resp, reg_rd_resp_io, reg_rd_resp_eth_if;
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reg_data_t reg_rd_data, reg_rd_data_io, reg_rd_data_eth_if;
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axil_regport_master #(
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.DWIDTH (REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64)
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.AWIDTH (REG_AWIDTH_MISC), // Width of the address bus
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.WRBASE (0), // Write address base
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.RDBASE (0), // Read address base
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.TIMEOUT (10) // log2(timeout). Read will timeout after (2^TIMEOUT - 1) cycles
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) axil_regport_master_i (
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// Clock and reset
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.s_axi_aclk (m_axi_misc_v[lane].clk),
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.s_axi_aresetn (!m_axi_misc_v[lane].rst),
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`AXI4LITE_PORT_ASSIGN_NR(s_axi,m_axi_misc_v[lane])
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// Register port: Write port (domain: reg_clk)
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.reg_clk (bus_clk),
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.reg_wr_req (reg_wr_req),
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.reg_wr_addr (reg_wr_addr),
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.reg_wr_data (reg_wr_data),
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.reg_wr_keep (/*unused*/),
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// Register port: Read port (domain: reg_clk)
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.reg_rd_req (reg_rd_req),
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.reg_rd_addr (reg_rd_addr),
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.reg_rd_resp (reg_rd_resp),
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.reg_rd_data (reg_rd_data)
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);
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// Regport Mux for response
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regport_resp_mux #(
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.WIDTH (REG_DWIDTH),
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.NUM_SLAVES (2)
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) regport_resp_mux_i (
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.clk(bus_clk), .reset(bus_rst),
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.sla_rd_resp({reg_rd_resp_eth_if, reg_rd_resp_io}),
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.sla_rd_data({reg_rd_data_eth_if, reg_rd_data_io}),
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.mst_rd_resp(reg_rd_resp), .mst_rd_data(reg_rd_data)
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);
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//---------------------------------------
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// MGT IO Core
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//---------------------------------------
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localparam MGT_W = (IS100GBE) ? 512 : 64;
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localparam MGT_USER_W = $clog2(MGT_W/8)+1;
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// The Clocking for the MGT interfaces comes from the MGT Wrapper
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// depending on the bus it may change.
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logic mgt_rst, mgt_clk;
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AxiStreamIf #(.DATA_WIDTH(MGT_W),.USER_WIDTH(MGT_USER_W))
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mgt_tx(mgt_clk, mgt_rst);
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AxiStreamIf #(.DATA_WIDTH(MGT_W),.USER_WIDTH(MGT_USER_W),.TKEEP(0))
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mgt_rx(mgt_clk, mgt_rst);
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logic mgt_pause_req;
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logic [3:0] tx_p_lane;
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logic [3:0] tx_n_lane;
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if (IS10GBE[lane]) begin
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// Single lane case:
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assign tx_p[lane] = tx_p_lane[lane];
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assign tx_n[lane] = tx_n_lane[lane];
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end else if (IS100GBE[lane] || ISAURORA[lane]) begin
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// Multi lane case:
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assign tx_p = tx_p_lane;
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assign tx_n = tx_n_lane;
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end
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x4xx_mgt_io_core #(
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.PROTOCOL (PROTOCOL[lane]),
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.REG_BASE (REG_BASE_SFP_IO),
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.REG_DWIDTH (REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64)
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.REG_AWIDTH (REG_AWIDTH_MISC), // Width of the address bus
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.PORTNUM (PORTNUM),
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.LANENUM (lane)
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) x4xx_mgt_io_core_i (
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// Must reset all channels on quad when QSFP GTX core is reset
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.areset (areset),
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.mgt_rst (mgt_rst),
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.mgt_clk (mgt_clk),
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.clk100 (clk100),
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.bus_rst (bus_rst),
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.bus_clk (bus_clk),
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.refclk_p (refclk_p),
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.refclk_n (refclk_n),
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.tx_p (tx_p_lane),
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.tx_n (tx_n_lane),
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.rx_p (rx_p),
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.rx_n (rx_n),
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// Common signals (for single lane instances)
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.qpll0_reset (qpll0_reset_i[lane]),
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.qpll0_lock (qpll0_lock),
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.qpll0_clk (qpll0_clk),
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.qpll0_refclk (qpll0_refclk),
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.qpll1_reset (qpll1_reset_i[lane]),
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.qpll1_lock (qpll1_lock),
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.qpll1_clk (qpll1_clk),
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.qpll1_refclk (qpll1_refclk),
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// RegPort
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.reg_wr_req (reg_wr_req),
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.reg_wr_addr (reg_wr_addr),
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.reg_wr_data (reg_wr_data),
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.reg_rd_req (reg_rd_req),
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.reg_rd_addr (reg_rd_addr),
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.reg_rd_resp (reg_rd_resp_io),
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.reg_rd_data (reg_rd_data_io),
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// AxiLite
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.m_axi_mac (m_axi_mac[lane]),
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// Pause
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.mgt_pause_req (mgt_pause_req),
|
||||
// Data
|
||||
.mgt_tx (mgt_tx),
|
||||
.mgt_rx (mgt_rx),
|
||||
|
||||
// Misc.
|
||||
.rx_rec_clk_out (rx_rec_clk_out_i[lane]),
|
||||
.port_info (port_info[lane]),
|
||||
.link_up (link_up[lane]),
|
||||
.activity (activity[lane])
|
||||
);
|
||||
|
||||
|
||||
if (IS100GBE[lane] || IS10GBE[lane]) begin : eth_port
|
||||
|
||||
//---------------------------------------
|
||||
// Ethernet IPv4 Interface for CHDR
|
||||
//---------------------------------------
|
||||
|
||||
// Option to use a bigger FIFO for 100GBe.
|
||||
// This is address width so +1 doubles the size +2 quadruples it.
|
||||
localparam CHDR_FIFO_SIZE = (IS100GBE[lane]) ? BYTE_MTU+2 : BYTE_MTU;
|
||||
|
||||
AxiStreamIf #(.DATA_WIDTH(CPU_W), .USER_WIDTH(CPU_USER_W), .TUSER(0))
|
||||
c2e (s_axi.clk, s_axi.rst);
|
||||
AxiStreamIf #(.DATA_WIDTH(CPU_W), .USER_WIDTH(CPU_USER_W), .TUSER(0))
|
||||
e2c (s_axi.clk, s_axi.rst);
|
||||
|
||||
localparam PAUSE_EN = (IS100GBE[lane]) ? 1 : 0;
|
||||
|
||||
// Ethernet interface
|
||||
// (1) routes the packet to CHDR/CPU
|
||||
// (2) implements a wrap back (eth_tx/eth_rx)
|
||||
eth_ipv4_interface #(
|
||||
.PROTOVER (RFNOC_PROTOVER),
|
||||
.CPU_FIFO_SIZE (BYTE_MTU),
|
||||
.CHDR_FIFO_SIZE (CHDR_FIFO_SIZE),
|
||||
.NODE_INST (0),
|
||||
.BASE (REG_BASE_ETH_SWITCH),
|
||||
.PREAMBLE_BYTES (0),
|
||||
.ADD_SOF (0),
|
||||
.SYNC (0), // c2e/e2c don't use the same clock as eth_tx/eth_rx
|
||||
.PAUSE_EN (PAUSE_EN),
|
||||
.ENET_W (MGT_W),
|
||||
.CPU_W (CPU_W),
|
||||
.CHDR_W (CHDR_W)
|
||||
) eth_ipv4_interface_i (
|
||||
.bus_clk (bus_clk),
|
||||
.bus_rst (bus_rst),
|
||||
.device_id (device_id),
|
||||
.reg_wr_req (reg_wr_req),
|
||||
.reg_wr_addr (reg_wr_addr),
|
||||
.reg_wr_data (reg_wr_data),
|
||||
.reg_rd_req (reg_rd_req),
|
||||
.reg_rd_addr (reg_rd_addr),
|
||||
.reg_rd_resp (reg_rd_resp_eth_if),
|
||||
.reg_rd_data (reg_rd_data_eth_if),
|
||||
.eth_pause_req (mgt_pause_req),
|
||||
.eth_tx (mgt_tx),
|
||||
.eth_rx (mgt_rx),
|
||||
.e2v (e2v[lane]),
|
||||
.v2e (v2e[lane]),
|
||||
.e2c (e2c),
|
||||
.c2e (c2e),
|
||||
.my_udp_chdr_port (/* unused */),
|
||||
.my_ip (/* unused */),
|
||||
.my_mac (/* unused */)
|
||||
);
|
||||
|
||||
axi_eth_dma axi_eth_dma_i (
|
||||
.c2e (c2e),
|
||||
.e2c (e2c),
|
||||
.s_axi_eth_dma (m_axi_dma[lane]),
|
||||
.axi_hp (axi_hp_dma[lane]),
|
||||
.eth_tx_irq (eth_tx_irq[lane]),
|
||||
.eth_rx_irq (eth_rx_irq[lane])
|
||||
);
|
||||
|
||||
end : eth_port else begin : not_eth
|
||||
|
||||
//---------------------------------------
|
||||
// Terminate DMA for Unused Ethernet
|
||||
//---------------------------------------
|
||||
|
||||
// Set unused ETH_DMA ports to default value
|
||||
always_comb begin
|
||||
m_axi_dma[lane].drive_read_resp(.resp(SLVERR),.data(0));
|
||||
m_axi_dma[lane].drive_write_resp(.resp(SLVERR));
|
||||
m_axi_dma[lane].arready = 1'b1;
|
||||
m_axi_dma[lane].awready = 1'b1;
|
||||
m_axi_dma[lane].wready = 1'b1;
|
||||
|
||||
axi_hp_dma[lane].drive_read_idle();
|
||||
axi_hp_dma[lane].drive_aw_idle();
|
||||
axi_hp_dma[lane].drive_w_idle();
|
||||
axi_hp_dma[lane].bready = 1'b0;
|
||||
axi_hp_dma[lane].rready = 1'b0;
|
||||
|
||||
mgt_pause_req = 0'b0;
|
||||
|
||||
eth_rx_irq[lane] = 1'b0;
|
||||
eth_tx_irq[lane] = 1'b0;
|
||||
|
||||
reg_rd_resp_eth_if = 1'b0;
|
||||
reg_rd_data_eth_if = 'h0;
|
||||
end
|
||||
|
||||
if (ISAURORA[lane]) begin : aurora_port
|
||||
|
||||
//---------------------------------------
|
||||
// Aurora
|
||||
//---------------------------------------
|
||||
|
||||
Aurora_not_yet_supported();
|
||||
|
||||
// if MGT_W and CHDR_W mismatch figure out what to do
|
||||
always_comb begin
|
||||
e2v[lane].tdata = mgt_rx.tdata;
|
||||
e2v[lane].tuser = 'b0;
|
||||
e2v[lane].tkeep = 'b1;
|
||||
e2v[lane].tlast = mgt_rx.tlast;
|
||||
e2v[lane].tvalid = mgt_rx.tvalid;
|
||||
mgt_rx.tready = e2v[lane].tready;
|
||||
|
||||
mgt_tx.tdata = v2e[lane].tdata;
|
||||
mgt_tx.tuser = 'b0;
|
||||
mgt_tx.tkeep = 'b1;
|
||||
mgt_tx.tlast = v2e[lane].tlast;
|
||||
mgt_tx.tvalid = v2e[lane].tvalid;
|
||||
v2e[lane].tready = mgt_tx.tready;
|
||||
end
|
||||
|
||||
end else begin : inactive_port
|
||||
|
||||
//---------------------------------------
|
||||
// Disabled Port
|
||||
//---------------------------------------
|
||||
|
||||
always_comb begin
|
||||
e2v[lane].tdata = 'b0;
|
||||
e2v[lane].tuser = 'b0;
|
||||
e2v[lane].tkeep = 'b1;
|
||||
e2v[lane].tlast = 1'b0;
|
||||
e2v[lane].tvalid = 1'b0;
|
||||
mgt_rx.tready = 1'b1;
|
||||
|
||||
mgt_tx.tdata = 'b0;
|
||||
mgt_tx.tuser = 'b0;
|
||||
mgt_tx.tkeep = 'b1;
|
||||
mgt_tx.tlast = 1'b0;
|
||||
mgt_tx.tvalid = 1'b0;
|
||||
v2e[lane].tready = 1'b1;
|
||||
end
|
||||
|
||||
end : inactive_port
|
||||
end : not_eth
|
||||
end : lane_loop
|
||||
end : mgt_lanes
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user