fpga: x400: Add support for X410 motherboard FPGA
Co-authored-by: Andrew Moch <Andrew.Moch@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Michael Auchter <michael.auchter@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Hector Rubio <hrubio@ni.com> Original-commit: 6d3765605262016a80f71e36357f749ea35cbe5a
This commit is contained in:
Wade Fife
committed by
Aaron Rossetto
Aaron Rossetto
co-authored by
Andrew Moch
Daniel Jepson
Javier Valenzuela
Joerg Hofrichter
Kumaran Subramoniam
Max Köhler
Michael Auchter
Paul Butler
Hector Rubio
Andrew Moch
Daniel Jepson
Javier Valenzuela
Joerg Hofrichter
Kumaran Subramoniam
Max Köhler
Michael Auchter
Paul Butler
Hector Rubio
parent
bfef20ea45
commit
61782b02d7
@@ -0,0 +1,426 @@
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//
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// Copyright 2021 Ettus Research, A National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: x4xx_pps_sync
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//
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// Description:
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//
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// This module encapsulates the PPS handling and the related LMK SYNC signal.
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//
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// Parameters:
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//
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// SIMULATION : When true, lowers 10 MHz PPS base reference clock to 10 kHz
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// to shorten simulation run time.
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//
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`default_nettype none
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module x4xx_pps_sync #(
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parameter SIMULATION = 0
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) (
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// clock and reset
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input wire base_ref_clk, // BRC
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input wire pll_ref_clk, // PRC
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input wire ctrl_clk, // CC
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input wire radio_clk, // RC
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input wire brc_rst,
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// PPS
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input wire pps_in, // BRC domain
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output wire pps_out_brc,
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output reg pps_out_rc = 1'b0,
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// LMK control signal
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output reg sync = 1'b0,
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// Control signals (CC domain)
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input wire [1:0] pps_select,
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input wire pll_sync_trigger,
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input wire [7:0] pll_sync_delay,
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output wire pll_sync_done,
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input wire [7:0] pps_brc_delay,
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input wire [25:0] pps_prc_delay,
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input wire [1:0] prc_rc_divider,
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input wire pps_rc_enabled,
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//signal for debugging
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output wire [1:0] debug
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);
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`include "regmap/global_regs_regmap_utils.vh"
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//---------------------------------------------------------------------------
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// PPS Generation and Capturing (BRC domain)
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//---------------------------------------------------------------------------
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// Divide 10 MHz to 10 kHz in case test mode is activated
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localparam FREQUENCY_10M = SIMULATION ? 32'd10_000 : 32'd10_000_000;
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localparam FREQUENCY_25M = 32'd25_000_000;
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// Generate internal PPS signals, each with a 25% duty cycle, based on
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// the different Reference Clock rates. Only one will be used at a time.
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// Available base reference clock rates are: 10 MHz, 25 MHz
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wire pps_int_10mhz_brc;
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pps_generator #(
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.CLK_FREQ (FREQUENCY_10M),
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.DUTY_CYCLE (25),
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.PIPELINE ("OUT")
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) pps_generator_10mhz (
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.clk (base_ref_clk),
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.reset (1'b0),
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.pps (pps_int_10mhz_brc)
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);
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wire pps_int_25mhz_brc;
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pps_generator #(
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.CLK_FREQ (FREQUENCY_25M),
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.DUTY_CYCLE (25),
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.PIPELINE ("OUT")
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) pps_generator_25mhz (
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.clk (base_ref_clk),
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.reset (1'b0),
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.pps (pps_int_25mhz_brc)
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);
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// Capture the external PPSs with a FF before sending them to the mux. To be
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// safe, we double-synchronize the external signals. If we meet timing (which
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// we should) then this is a two-cycle delay. If we don't meet timing, then
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// it's 1-2 cycles and our system timing is thrown off--but at least our
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// downstream logic doesn't go metastable!
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wire pps_ext_brc;
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synchronizer #(
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.FALSE_PATH_TO_IN (0)
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) synchronizer_pps_ext (
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.clk (base_ref_clk),
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.rst (1'b0),
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.in (pps_in),
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.out (pps_ext_brc)
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);
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// Synchronize the select bits over to the reference clock as well. Note that this is
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// a vector, so we could have some invalid values creep through when changing.
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// See the note below as to why this is safe.
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wire [1:0] pps_select_brc;
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synchronizer #(
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.FALSE_PATH_TO_IN (1),
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.WIDTH (2)
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) synchronizer_pps_select (
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.clk (base_ref_clk),
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.rst (1'b0),
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.in (pps_select),
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.out (pps_select_brc)
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);
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// PPS MUX - selects internal or external PPS.
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reg pps_brc = 1'b0;
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always @(posedge base_ref_clk) begin
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// It is possible when the vector is being double-synchronized to the
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// reference clock domain that there could be multiple bits asserted
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// simultaneously. This is not problematic because the order of operations
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// in the following selection mux should take over and only one PPS should
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// win. This could result in glitches, but that is expected during ANY PPS
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// switchover since the switch is performed asynchronously to the PPS
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// signal.
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case (pps_select_brc)
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PPS_INT_10MHZ: begin
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pps_brc <= pps_int_10mhz_brc;
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end
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PPS_INT_25MHZ: begin
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pps_brc <= pps_int_25mhz_brc;
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end
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default: begin
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pps_brc <= pps_ext_brc;
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end
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endcase
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end
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// forward BRC based PPS to output
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assign pps_out_brc = pps_brc;
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//---------------------------------------------------------------------------
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// LMK sync generation (BRC domain)
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//---------------------------------------------------------------------------
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// Detect rising edge of PPS
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reg pps_brc_delayed;
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wire pps_rising_edge_brc;
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always @(posedge base_ref_clk) begin
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pps_brc_delayed <= pps_brc;
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end
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assign pps_rising_edge_brc = pps_brc & ~pps_brc_delayed;
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// Transfer control signals to internal clock domain
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wire pll_sync_trigger_brc;
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synchronizer #(
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.FALSE_PATH_TO_IN (1)
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) synchronizer_sync_trigger (
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.clk (base_ref_clk),
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.rst (1'b0),
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.in (pll_sync_trigger),
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.out (pll_sync_trigger_brc)
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);
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// There is no data coherency guaranteed by this synchronizer, but this is
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// not required. The information is derived in the same clock domain as the
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// sync trigger. Both information in the worst case arrive in the same clock
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// cycle. In the state machine the trigger is changing the state to ARMED.
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// The delay value is required in the ARMED state. This way there is one more
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// clock cycle for this synchronizer to propagate the correct value of all
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// bits.
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wire [7:0] pll_sync_delay_brc;
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synchronizer #(
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.FALSE_PATH_TO_IN (1),
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.WIDTH (8)
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) synchronizer_sync_delay (
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.clk (base_ref_clk),
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.rst (1'b0),
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.in (pll_sync_delay),
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.out (pll_sync_delay_brc)
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);
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// Synchronization state machine
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localparam IDLE = 2'd0;
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localparam ARMED = 2'd1;
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localparam COUNT = 2'd2;
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localparam DONE = 2'd3;
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reg [7:0] delay_counter_brc = 8'd0;
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reg [1:0] state = IDLE;
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reg pll_sync_done_brc = 1'b0;
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reg sync_int = 1'b0;
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always @(posedge base_ref_clk) begin
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if (brc_rst) begin
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sync_int <= 1'b0;
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pll_sync_done_brc <= 1'b0;
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state <= IDLE;
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end
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else begin
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case (state)
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IDLE: begin
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// Wait for trigger from control interface
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if (pll_sync_trigger_brc) begin
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state <= ARMED;
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end
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end
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ARMED: begin
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// Wait for the rising edge of PPS and reset counter
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delay_counter_brc <= pll_sync_delay_brc;
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if (pps_rising_edge_brc) begin
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state <= COUNT;
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end
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end
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// Delay assertion of sync signal by the given number of cycles
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COUNT: begin
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delay_counter_brc <= delay_counter_brc - 1;
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if (delay_counter_brc == 0) begin
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state <= DONE;
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sync_int <= 1'b1;
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end
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end
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// Issue done signal until the trigger is released
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DONE: begin
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sync_int <= 1'b0;
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pll_sync_done_brc <= 1'b1;
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if (pll_sync_trigger_brc == 0) begin
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state <= IDLE;
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pll_sync_done_brc <= 1'b0;
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end
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end
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// In case we run into an undefined state
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default: begin
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state <= IDLE;
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end
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endcase
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end
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end
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// Transfer done signal back to ctrl_clk domain
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synchronizer #(
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.FALSE_PATH_TO_IN (1)
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) synchronizer_pll_sync_done (
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.clk (ctrl_clk),
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.rst (1'b0),
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.in (pll_sync_done_brc),
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.out (pll_sync_done)
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);
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// Sync signal is captured at falling edge of clock to ensure hold time
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always @(negedge base_ref_clk) begin
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sync <= sync_int;
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end
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//---------------------------------------------------------------------------
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// PPS clock domain crossings
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//---------------------------------------------------------------------------
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// In the section below the PPS crosses multiple clock domains.
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// From the generation in BRC clock domain we transfer the signal over to
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// PRC using the aligned edge of the external LMK IC.
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// Afterwards we use the integer clock multiplier between PRC and RC to
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// get the PPS trigger to the radio clock domain.
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// BRC --\____/----\____/----\____/----\____/----\____/----\____/
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// PRC ___/---\___/---\___/---\___/---\___/---\___/---\___/---\__
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// RC -\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\
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// | aligned edge
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// PPS (BRC) __/--------------------------------------------------------
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// PPS (BRC delayed) ___________________/-------------------------------
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// Has to shift PPS to start on aligned edge.
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//
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// PPS (PRC) __________________________________________/----------------
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// |------------->| 2 PRC cycles
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// 2 stage synchronizer = 2 PRC cycle delay on aligned edge
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//
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// PPS (PRC delayed) __________/----------------------------------------
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// |------------------
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// ------------------------->| up to PRC frequency cycles
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// Shifts PPS pulse by up to 1 second (PPS period) to be present in the
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// clock cycle before the aligned edge.
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//
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// PPS (RC) ___________________________/-\_____________________________
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// |------->| RC clock multiplier based cycles
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// Number of sync registers depends on clock multiplier between PRC and
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// RC to align PPS signal with aligned edge. Additional logic to restore
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// a one cycle long pulse from PPS signal with 25% duty cycle.
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//---------------------------------------------------------------------------
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// PPS delay (BRC domain)
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//---------------------------------------------------------------------------
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// This shift register delays the PPS trigger until the appearance of
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// the aligned edge of BRC and PRC.
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// This delay has to incorporate the delay of the state machine above from
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// pps to sync output, the delay of the LMK chip from sync edge to aligned
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// edge and delay setting applied to the sync signal. Be sure to reduce the
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// number by 1 at the end to account for the final register.
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wire [7:0] pps_brc_delay_brc;
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synchronizer #(
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.FALSE_PATH_TO_IN (1),
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.WIDTH (8)
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) synchronizer_pps_brc_delay (
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.clk (base_ref_clk),
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.rst (1'b0),
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.in (pps_brc_delay),
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.out (pps_brc_delay_brc)
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);
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reg [255:0] pps_shift_reg_brc = 256'b0;
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reg pps_delayed_brc = 1'b0;
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always @(posedge base_ref_clk) begin
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pps_shift_reg_brc <= {pps_shift_reg_brc[254:0], pps_brc};
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pps_delayed_brc <= pps_shift_reg_brc[pps_brc_delay_brc];
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end
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//---------------------------------------------------------------------------
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// PPS clock domain crossing
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//---------------------------------------------------------------------------
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// On the aligned edge of BRC and PRC this synchronizer is just a two stage
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// delay into the PRC domain as the edges occur at the same time the tools
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// should make sure we close timing on this edge
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wire pps_prc;
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synchronizer #(
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.FALSE_PATH_TO_IN (0)
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) synchronizer_pps_prc (
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.clk (pll_ref_clk),
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.rst (1'b0),
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.in (pps_delayed_brc),
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.out (pps_prc)
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);
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//---------------------------------------------------------------------------
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// PPS delay (PRC)
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//---------------------------------------------------------------------------
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// Delay the PPS signal in PRC domain by a specified amount to align with
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// other devices (max delay = 1 sec = next occurrence of pps rising edge).
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// Make sure that the initial count value accounts for the two stage
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// synchronizer from BRC to PRC, the final register upon counter reaches
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// its final value and it has to be one cycle earlier than the aligned edge
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// to get transferred to radio clock afterwards.
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wire [25:0] pps_prc_delay_prc;
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synchronizer #(
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.FALSE_PATH_TO_IN (1),
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.WIDTH (26)
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) synchronizer_pps_prc_delay (
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.clk (pll_ref_clk),
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.rst (1'b0),
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.in (pps_prc_delay),
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.out (pps_prc_delay_prc)
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);
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reg [25:0] delay_counter_prc = 26'b0;
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reg pps_delayed_prc = 1'b0;
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reg pps_prc_delayed = 1'b0;
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always @(posedge pll_ref_clk) begin
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// Disable delayed rising edge by default
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pps_delayed_prc <= 1'b0;
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pps_prc_delayed <= pps_prc;
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// Reset counter on rising edge
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if (pps_prc & ~pps_prc_delayed) begin
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delay_counter_prc <= pps_prc_delay_prc;
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end
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else begin
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if (delay_counter_prc != 0) begin
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delay_counter_prc <= delay_counter_prc - 1;
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end
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if (delay_counter_prc == 1) begin
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pps_delayed_prc <= 1'b1;
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end
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end
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end
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//---------------------------------------------------------------------------
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// PPS PRC to radio clock
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//---------------------------------------------------------------------------
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// Tiny shift register to account for the clock multiplier between prc and
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// rc. The divider has to account for the output register and the shift
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// register.
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wire [1:0] prc_rc_divider_rc;
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wire pps_rc_enabled_rc;
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synchronizer #(
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.FALSE_PATH_TO_IN (1),
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.WIDTH (2)
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) synchronizer_prc_rc_divider (
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.clk (radio_clk),
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.rst (1'b0),
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.in (prc_rc_divider),
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.out (prc_rc_divider_rc)
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);
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synchronizer #(
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.FALSE_PATH_TO_IN (1)
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) synchronizer_pps_rc_enabled (
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.clk (radio_clk),
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.rst (1'b0),
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.in (pps_rc_enabled),
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.out (pps_rc_enabled_rc)
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);
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reg [3:0] pps_shift_reg_rc = 4'b0;
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always @(posedge radio_clk) begin
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pps_shift_reg_rc <= {pps_shift_reg_rc[2:0], pps_delayed_prc};
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// Restoring a one clock cycle pulse by feeding back to output value.
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pps_out_rc <= pps_shift_reg_rc[prc_rc_divider_rc] & ~pps_out_rc & pps_rc_enabled_rc;
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end
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//---------------------------------------------------------------------------
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// Debug assignment
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//---------------------------------------------------------------------------
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assign debug[0] = pps_delayed_brc;
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assign debug[1] = pps_delayed_prc;
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endmodule
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`default_nettype wire
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