fpga: x400: Add support for X410 motherboard FPGA
Co-authored-by: Andrew Moch <Andrew.Moch@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Michael Auchter <michael.auchter@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Hector Rubio <hrubio@ni.com> Original-commit: 6d3765605262016a80f71e36357f749ea35cbe5a
This commit is contained in:
Wade Fife
committed by
Aaron Rossetto
Aaron Rossetto
co-authored by
Andrew Moch
Daniel Jepson
Javier Valenzuela
Joerg Hofrichter
Kumaran Subramoniam
Max Köhler
Michael Auchter
Paul Butler
Hector Rubio
Andrew Moch
Daniel Jepson
Javier Valenzuela
Joerg Hofrichter
Kumaran Subramoniam
Max Köhler
Michael Auchter
Paul Butler
Hector Rubio
parent
bfef20ea45
commit
61782b02d7
@@ -0,0 +1,357 @@
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//
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// Copyright 2021 Ettus Research, A National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: x4xx_core_common
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//
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// Description:
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//
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// This module contains the common core infrastructure for RFNoC, such as the
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// motherboard registers and timekeeper.
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//
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// Parameters:
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//
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// CHDR_CLK_RATE : Rate of rfnoc_chdr_clk in Hz
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// CHDR_W : CHDR protocol width
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// RFNOC_PROTOVER : RFNoC protocol version (major in most-significant byte,
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// Minor is least significant byte)
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// PCIE_PRESENT : Indicates if PCIe is present in this image
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//
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`default_nettype none
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module x4xx_core_common #(
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parameter CHDR_CLK_RATE = 200000000,
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parameter CHDR_W = 64,
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parameter RFNOC_PROTOVER = {8'd1, 8'd0},
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parameter PCIE_PRESENT = 0
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) (
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// Clocks and resets
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input wire radio_clk,
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input wire radio_rst,
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input wire rfnoc_chdr_clk,
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input wire rfnoc_chdr_rst,
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input wire rfnoc_ctrl_clk,
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input wire rfnoc_ctrl_rst,
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// Ctrlport master interface from AXI
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input wire ctrlport_rst,
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input wire ctrlport_clk,
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input wire s_ctrlport_req_wr,
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input wire s_ctrlport_req_rd,
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input wire [19:0] s_ctrlport_req_addr,
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input wire [ 9:0] s_ctrlport_req_portid,
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input wire [15:0] s_ctrlport_req_rem_epid,
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input wire [ 9:0] s_ctrlport_req_rem_portid,
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input wire [31:0] s_ctrlport_req_data,
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input wire [ 3:0] s_ctrlport_req_byte_en,
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input wire s_ctrlport_req_has_time,
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input wire [63:0] s_ctrlport_req_time,
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output wire s_ctrlport_resp_ack,
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output wire [ 1:0] s_ctrlport_resp_status,
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output wire [31:0] s_ctrlport_resp_data,
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// PPS (top-level inputs)
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input wire pps_radioclk,
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// PPS and clock control (Domain: rfnoc_ctrl_clk)
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output wire [ 1:0] pps_select,
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output wire [ 1:0] trig_io_select,
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output wire pll_sync_trigger,
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output wire [ 7:0] pll_sync_delay,
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input wire pll_sync_done,
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output wire [ 7:0] pps_brc_delay,
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output wire [25:0] pps_prc_delay,
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output wire [ 1:0] prc_rc_divider,
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output wire pps_rc_enabled,
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// Timekeeper (Domain: radio_clk)
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input wire [ 7:0] radio_spc,
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output wire [63:0] radio_time,
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input wire sample_rx_stb,
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// GPIO to DIO board (Domain: rfnoc_ctrl_clk)
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output wire [11:0] gpio_en_a,
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output wire [11:0] gpio_en_b,
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// GPIO to DIO board (async)
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input wire [11:0] gpio_in_a,
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input wire [11:0] gpio_in_b,
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output wire [11:0] gpio_out_a,
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output wire [11:0] gpio_out_b,
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// GPIO to application (Domain: rfnoc_ctrl_clk)
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output wire [11:0] gpio_in_fabric_a,
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output wire [11:0] gpio_in_fabric_b,
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input wire [11:0] gpio_out_fabric_a,
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input wire [11:0] gpio_out_fabric_b,
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// Misc (Domain: rfnoc_ctrl_clk)
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input wire [31:0] qsfp_port_0_0_info,
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input wire [31:0] qsfp_port_0_1_info,
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input wire [31:0] qsfp_port_0_2_info,
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input wire [31:0] qsfp_port_0_3_info,
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input wire [31:0] qsfp_port_1_0_info,
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input wire [31:0] qsfp_port_1_1_info,
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input wire [31:0] qsfp_port_1_2_info,
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input wire [31:0] qsfp_port_1_3_info,
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output wire [15:0] device_id,
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output wire mfg_test_en_fabric_clk,
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output wire mfg_test_en_gty_rcv_clk,
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input wire fpga_aux_ref,
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// Version (Constant)
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// Each component consists of a 96-bit vector (refer to versioning_utils.vh)
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input wire [64*96-1:0] version_info
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);
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`include "../../lib/rfnoc/core/ctrlport.vh"
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`include "regmap/core_regs_regmap_utils.vh"
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//---------------------------------------------------------------------------
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// AXI4-Lite to ctrlport
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//---------------------------------------------------------------------------
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// Ctrlport master interface (domain: rfnoc_ctrl_clk)
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wire m_req_wr;
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wire m_req_rd;
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wire [CTRLPORT_ADDR_W-1:0] m_req_addr;
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wire [CTRLPORT_DATA_W-1:0] m_req_data;
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wire m_resp_ack;
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wire [ CTRLPORT_STS_W-1:0] m_resp_status;
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wire [CTRLPORT_DATA_W-1:0] m_resp_data;
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// Split ctrlport for multiple endpoints (domain: rfnoc_ctrl_clk)
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wire timekeeper_req_wr, versioning_req_wr, global_regs_req_wr, dio_req_wr;
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wire timekeeper_req_rd, versioning_req_rd, global_regs_req_rd, dio_req_rd;
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wire [CTRLPORT_ADDR_W-1:0] timekeeper_req_addr, versioning_req_addr, global_regs_req_addr, dio_req_addr;
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wire [CTRLPORT_DATA_W-1:0] timekeeper_req_data, versioning_req_data, global_regs_req_data, dio_req_data;
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wire timekeeper_resp_ack, versioning_resp_ack, global_regs_resp_ack, dio_resp_ack;
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wire [ CTRLPORT_STS_W-1:0] timekeeper_resp_status, versioning_resp_status, global_regs_resp_status, dio_resp_status;
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wire [CTRLPORT_DATA_W-1:0] timekeeper_resp_data, versioning_resp_data, global_regs_resp_data, dio_resp_data;
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ctrlport_clk_cross ctrlport_clk_cross_i (
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.rst (ctrlport_rst),
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.s_ctrlport_clk (ctrlport_clk),
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.s_ctrlport_req_wr (s_ctrlport_req_wr),
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.s_ctrlport_req_rd (s_ctrlport_req_rd),
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.s_ctrlport_req_addr (s_ctrlport_req_addr),
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.s_ctrlport_req_portid (s_ctrlport_req_portid),
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.s_ctrlport_req_rem_epid (s_ctrlport_req_rem_epid),
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.s_ctrlport_req_rem_portid (s_ctrlport_req_rem_portid),
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.s_ctrlport_req_data (s_ctrlport_req_data),
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.s_ctrlport_req_byte_en (s_ctrlport_req_byte_en),
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.s_ctrlport_req_has_time (s_ctrlport_req_has_time),
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.s_ctrlport_req_time (s_ctrlport_req_time),
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.s_ctrlport_resp_ack (s_ctrlport_resp_ack),
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.s_ctrlport_resp_status (s_ctrlport_resp_status),
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.s_ctrlport_resp_data (s_ctrlport_resp_data),
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.m_ctrlport_clk (rfnoc_ctrl_clk),
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.m_ctrlport_req_wr (m_req_wr),
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.m_ctrlport_req_rd (m_req_rd),
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.m_ctrlport_req_addr (m_req_addr),
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.m_ctrlport_req_portid (),
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.m_ctrlport_req_rem_epid (),
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.m_ctrlport_req_rem_portid (),
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.m_ctrlport_req_data (m_req_data),
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.m_ctrlport_req_byte_en (),
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.m_ctrlport_req_has_time (),
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.m_ctrlport_req_time (),
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.m_ctrlport_resp_ack (m_resp_ack),
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.m_ctrlport_resp_status (m_resp_status),
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.m_ctrlport_resp_data (m_resp_data)
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);
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ctrlport_splitter #(
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.NUM_SLAVES (4)
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) ctrlport_splitter_i (
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.ctrlport_clk (rfnoc_ctrl_clk),
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.ctrlport_rst (rfnoc_ctrl_rst),
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.s_ctrlport_req_wr (m_req_wr),
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.s_ctrlport_req_rd (m_req_rd),
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.s_ctrlport_req_addr (m_req_addr),
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.s_ctrlport_req_data (m_req_data),
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.s_ctrlport_req_byte_en (4'hF),
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.s_ctrlport_req_has_time (1'b0),
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.s_ctrlport_req_time (64'h0),
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.s_ctrlport_resp_ack (m_resp_ack),
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.s_ctrlport_resp_status (m_resp_status),
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.s_ctrlport_resp_data (m_resp_data),
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.m_ctrlport_req_wr ({timekeeper_req_wr, versioning_req_wr, global_regs_req_wr, dio_req_wr}),
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.m_ctrlport_req_rd ({timekeeper_req_rd, versioning_req_rd, global_regs_req_rd, dio_req_rd}),
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.m_ctrlport_req_addr ({timekeeper_req_addr, versioning_req_addr, global_regs_req_addr, dio_req_addr}),
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.m_ctrlport_req_data ({timekeeper_req_data, versioning_req_data, global_regs_req_data, dio_req_data}),
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.m_ctrlport_req_byte_en (),
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.m_ctrlport_req_has_time (),
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.m_ctrlport_req_time (),
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.m_ctrlport_resp_ack ({timekeeper_resp_ack, versioning_resp_ack, global_regs_resp_ack, dio_resp_ack}),
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.m_ctrlport_resp_status ({timekeeper_resp_status, versioning_resp_status, global_regs_resp_status, dio_resp_status}),
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.m_ctrlport_resp_data ({timekeeper_resp_data, versioning_resp_data, global_regs_resp_data, dio_resp_data})
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);
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//--------------------------------------------------------------------
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// Global Registers
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// -------------------------------------------------------------------
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localparam NUM_TIMEKEEPERS = 1;
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x4xx_global_regs #(
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.REG_BASE (GLOBAL_REGS),
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.REG_SIZE (GLOBAL_REGS_SIZE),
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.CHDR_CLK_RATE (CHDR_CLK_RATE),
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.CHDR_W (CHDR_W),
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.RFNOC_PROTOVER (RFNOC_PROTOVER),
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.NUM_TIMEKEEPERS (NUM_TIMEKEEPERS),
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.PCIE_PRESENT (PCIE_PRESENT)
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) x4xx_global_regs_i (
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.s_ctrlport_clk (rfnoc_ctrl_clk),
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.s_ctrlport_rst (rfnoc_ctrl_rst),
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.s_ctrlport_req_wr (global_regs_req_wr),
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.s_ctrlport_req_rd (global_regs_req_rd),
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.s_ctrlport_req_addr (global_regs_req_addr),
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.s_ctrlport_req_data (global_regs_req_data),
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.s_ctrlport_resp_ack (global_regs_resp_ack),
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.s_ctrlport_resp_status (global_regs_resp_status),
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.s_ctrlport_resp_data (global_regs_resp_data),
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.rfnoc_chdr_clk (rfnoc_chdr_clk),
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.rfnoc_chdr_rst (rfnoc_chdr_rst),
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.pps_select (pps_select),
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.trig_io_select (trig_io_select),
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.pll_sync_trigger (pll_sync_trigger),
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.pll_sync_delay (pll_sync_delay),
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.pll_sync_done (pll_sync_done),
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.pps_brc_delay (pps_brc_delay),
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.pps_prc_delay (pps_prc_delay),
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.prc_rc_divider (prc_rc_divider),
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.pps_rc_enabled (pps_rc_enabled),
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.qsfp_port_0_0_info (qsfp_port_0_0_info),
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.qsfp_port_0_1_info (qsfp_port_0_1_info),
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.qsfp_port_0_2_info (qsfp_port_0_2_info),
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.qsfp_port_0_3_info (qsfp_port_0_3_info),
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.qsfp_port_1_0_info (qsfp_port_1_0_info),
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.qsfp_port_1_1_info (qsfp_port_1_1_info),
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.qsfp_port_1_2_info (qsfp_port_1_2_info),
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.qsfp_port_1_3_info (qsfp_port_1_3_info),
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.mfg_test_en_fabric_clk (mfg_test_en_fabric_clk),
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.mfg_test_en_gty_rcv_clk (mfg_test_en_gty_rcv_clk),
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.fpga_aux_ref (fpga_aux_ref),
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.device_id (device_id)
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);
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//--------------------------------------------------------------------
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// Version Registers
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// -------------------------------------------------------------------
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x4xx_versioning_regs #(
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.REG_BASE (VERSIONING_REGS)
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) x4xx_versioning_regs_i (
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.s_ctrlport_clk (rfnoc_ctrl_clk),
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.s_ctrlport_rst (rfnoc_ctrl_rst),
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.s_ctrlport_req_wr (versioning_req_wr),
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.s_ctrlport_req_rd (versioning_req_rd),
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.s_ctrlport_req_addr (versioning_req_addr),
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.s_ctrlport_req_data (versioning_req_data),
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.s_ctrlport_resp_ack (versioning_resp_ack),
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.s_ctrlport_resp_status (versioning_resp_status),
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.s_ctrlport_resp_data (versioning_resp_data),
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.version_info (version_info)
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);
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//---------------------------------------------------------------------------
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// Timekeeper
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//---------------------------------------------------------------------------
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assign timekeeper_resp_status = CTRL_STS_OKAY;
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timekeeper #(
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.BASE_ADDR (TIMEKEEPER),
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.TIME_INCREMENT (0)
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) timekeeper_i (
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.tb_clk (radio_clk),
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.tb_rst (radio_rst),
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.s_ctrlport_clk (rfnoc_ctrl_clk),
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.s_ctrlport_req_wr (timekeeper_req_wr),
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.s_ctrlport_req_rd (timekeeper_req_rd),
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.s_ctrlport_req_addr (timekeeper_req_addr),
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.s_ctrlport_req_data (timekeeper_req_data),
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.s_ctrlport_resp_ack (timekeeper_resp_ack),
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.s_ctrlport_resp_data (timekeeper_resp_data),
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.time_increment (radio_spc),
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.sample_rx_stb (sample_rx_stb),
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.pps (pps_radioclk),
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.tb_timestamp (radio_time),
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.tb_timestamp_last_pps (),
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.tb_period_ns_q32 ()
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);
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//---------------------------------------------------------------------------
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// DIO
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//---------------------------------------------------------------------------
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x4xx_dio #(
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.REG_BASE (DIO),
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.REG_SIZE (DIO_SIZE)
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) x4xx_dio_i (
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.ctrlport_clk (rfnoc_ctrl_clk),
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.ctrlport_rst (rfnoc_ctrl_rst),
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.s_ctrlport_req_wr (dio_req_wr),
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.s_ctrlport_req_rd (dio_req_rd),
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.s_ctrlport_req_addr (dio_req_addr),
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.s_ctrlport_req_data (dio_req_data),
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.s_ctrlport_resp_ack (dio_resp_ack),
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.s_ctrlport_resp_status (dio_resp_status),
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.s_ctrlport_resp_data (dio_resp_data),
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.gpio_in_a (gpio_in_a),
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.gpio_in_b (gpio_in_b),
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.gpio_out_a (gpio_out_a),
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.gpio_out_b (gpio_out_b),
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.gpio_en_a (gpio_en_a),
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.gpio_en_b (gpio_en_b),
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.gpio_in_fabric_a (gpio_in_fabric_a),
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.gpio_in_fabric_b (gpio_in_fabric_b),
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.gpio_out_fabric_a (gpio_out_fabric_a),
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.gpio_out_fabric_b (gpio_out_fabric_b)
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);
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endmodule
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`default_nettype wire
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//XmlParse xml_on
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//<regmap name="CORE_REGS_REGMAP" readablestrobes="false" generatevhdl="true" ettusguidelines="true">
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// <info>
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// This is the map for the registers that the CORE_REGS window has access to
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// from the ARM_AXI_HPM0_FPD port.
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//
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// The registers contained here conform the mboard-regs node that MPM uses
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// to manage general FPGA control/status calls, such as versioning,
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// timekeeper, GPIO, etc.
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// </info>
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// <group name="CORE_REGS">
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// <window name="GLOBAL_REGS" offset="0x0" size="0xC00" targetregmap="GLOBAL_REGS_REGMAP">
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// <info>Window to access global registers in the FPGA.</info>
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// </window>
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// <window name="VERSIONING_REGS" offset="0xC00" size="0x400" targetregmap="VERSIONING_REGS_REGMAP">
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// <info>Window to access versioning registers in the FPGA.</info>
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// </window>
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// <window name="TIMEKEEPER" offset="0x1000" size="0x20">
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// <info>Window to access the timekeeper register map.</info>
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// </window>
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// <window name="DIO" offset="0x2000" size="0x20" targetregmap="DIO_REGMAP">
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// <info>Window to access the DIO register map.</info>
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// </window>
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// </group>
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//</regmap>
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//XmlParse xml_off
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