fpga: x400: Add support for X410 motherboard FPGA
Co-authored-by: Andrew Moch <Andrew.Moch@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Michael Auchter <michael.auchter@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Hector Rubio <hrubio@ni.com> Original-commit: 6d3765605262016a80f71e36357f749ea35cbe5a
This commit is contained in:
Wade Fife
committed by
Aaron Rossetto
Aaron Rossetto
co-authored by
Andrew Moch
Daniel Jepson
Javier Valenzuela
Joerg Hofrichter
Kumaran Subramoniam
Max Köhler
Michael Auchter
Paul Butler
Hector Rubio
Andrew Moch
Daniel Jepson
Javier Valenzuela
Joerg Hofrichter
Kumaran Subramoniam
Max Köhler
Michael Auchter
Paul Butler
Hector Rubio
parent
bfef20ea45
commit
61782b02d7
@@ -0,0 +1,436 @@
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--
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-- Copyright 2021 Ettus Research, a National Instruments Brand
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--
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-- SPDX-License-Identifier: LGPL-3.0-or-later
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--
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-- Module: tb_rf_reset_controller
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--
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-- Description:
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--
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-- Testbench for rf_reset_controller.
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--
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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library WORK;
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use WORK.PkgRFDC_REGS_REGMAP.all;
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entity tb_rf_reset_controller is
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end tb_rf_reset_controller;
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architecture RTL of tb_rf_reset_controller is
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component rf_reset_controller
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port (
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ConfigClk : in std_logic;
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DataClk : in std_logic;
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PllRefClk : in std_logic;
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RfClk : in std_logic;
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RfClk2x : in std_logic;
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DataClk2x : in std_logic;
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dAdcResetPulse : in std_logic;
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dDacResetPulse : in std_logic;
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dAdcDataOutReset_n : out std_logic;
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r2AdcFirReset_n : out std_logic;
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rAdcRfdcAxiReset_n : out std_logic;
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rAdcEnableData : out std_logic;
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rAdcGearboxReset_n : out std_logic;
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dDacDataInReset_n : out std_logic;
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r2DacFirReset_n : out std_logic;
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d2DacFirReset_n : out std_logic;
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rDacRfdcAxiReset_n : out std_logic;
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rDacGearboxReset_n : out std_logic;
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cSoftwareControl : in std_logic_vector(31 downto 0);
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cSoftwareStatus : out std_logic_vector(31 downto 0));
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end component;
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signal cSoftwareStatus : std_logic_vector(31 downto 0);
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signal r2AdcFirReset_n : std_logic;
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signal r2DacFirReset_n : std_logic;
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signal rAdcGearboxReset_n : std_logic;
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signal rDacGearboxReset_n : std_logic;
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signal cSoftwareControl : std_logic_vector(31 downto 0) := (others => '0');
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signal dAdcResetPulse : std_logic := '0';
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signal dDacResetPulse : std_logic := '0';
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constant kSwReset : std_logic := '0';
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constant kTimedReset : std_logic := '1';
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-- All constants mentioned below are number of the particular clock cycles
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-- PllRefClk period. For example, kDataClkCycles is the total number of
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-- DataClk cycles in the PllRefClk period.
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constant kDataClkCycles : integer := 2;
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constant kDataClk2xCycles : integer := 4;
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constant kRfClkCycles : integer := 3;
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constant kRfClk2xCycles : integer := 6;
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constant kConfigPer : time := 25 ns;
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-- Make sure the PllRefClk period is a least common multiple of all the other
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-- derived clock.
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constant kPllRefClkPer : time := 12 ns;
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constant kDataClkPer : time := kPllRefClkPer/2;
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constant kDataClk2xPer : time := kPllRefClkPer/4;
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constant kRfClkPer : time := kPllRefClkPer/3;
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constant kRfClk2xPer : time := kPllRefClkPer/6;
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signal pReset : boolean := false;
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signal dCount : integer := 0;
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signal d2Count : integer := 0;
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signal rCount : integer := 0;
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signal r2Count : integer := 0;
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signal StopSim : boolean;
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signal ConfigClk : std_logic := '1';
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signal RfClk : std_logic := '1';
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signal RfClk2x : std_logic := '1';
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signal DataClk : std_logic := '1';
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signal DataClk2x : std_logic := '1';
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signal PllRefClk : std_logic := '1';
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signal dAdcDataOutReset_n : std_logic := '0';
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signal dAdcDataOutResetDlyd_n : std_logic := '0';
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signal dDacDataInReset_n : std_logic := '0';
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signal dDacDataInResetDlyd_n : std_logic := '0';
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signal d2DacFirReset_n : std_logic := '0';
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signal d2DacFirResetDlyd_n : std_logic := '0';
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signal rAdcRfdcAxiReset_n : std_logic := '0';
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signal rAdcRfdcAxiResetDlyd_n : std_logic := '0';
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signal rDacRfdcAxiReset_n : std_logic := '0';
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signal rDacRfdcAxiResetDlyd_n : std_logic := '0';
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signal r2AdcFirResetDlyd_n : std_logic := '0';
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signal r2DacFirResetDlyd_n : std_logic := '0';
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signal ExpectedSwAdcResetDone : std_logic := '0';
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signal ExpectedAdcReset : std_logic := '0';
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signal ExpectedSwDacResetDone : std_logic := '0';
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signal ExpectedDacReset : std_logic := '0';
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signal ExpectedAxiAdcResetOut : std_logic := '0';
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signal ExpectedAxiDacResetOut : std_logic := '0';
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-- Make sure the wait time for reset done check is at least 10 ConfigClk
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-- cycles to account for all clock domain crossings. We also have some status
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-- check in the testbench which requires the wait to be additional ConfigClk
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-- cycles. This wait is in ConfigClk period.
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constant kResetDoneWait : positive := 10;
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procedure ClkWait(signal clk : in std_logic; X : positive := 1) is
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begin
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for i in 1 to X loop
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wait until rising_edge(clk);
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end loop;
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end procedure ClkWait;
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-- Check phase alignment of reset. We want to make sure the reset is asserted
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-- on the 1st rising clock edge after the rising edge of PllRefClk.
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procedure CheckAlignment(
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signal Clk : in std_logic; -- Synchronous reset clock
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signal Reset_n : in std_logic; -- Synchronous reset
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signal ResetDlyd_n : inout std_logic; -- Delayed synchronous reset
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signal PhaseCount : in integer; -- Phase count used to check alignment
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Message : string) is -- Assertion message
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begin
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-- Check if reset is asserted on the 1st Clk after the rising edge of
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-- PllRefClk.
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if falling_edge(Clk) then
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ResetDlyd_n <= Reset_n;
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if Reset_n = '0' and ResetDlyd_n = '1' then
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assert PhaseCount = 1
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report Message & " reset is not asserted in the expected time" severity error;
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end if;
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end if;
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end procedure CheckAlignment;
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-- Procedure to generate phase counter that is used to check the alignment of
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-- phase of all clocks related to PllRefClk.
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procedure PhaseCounter(
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signal Clk : in std_logic; -- Clock related to PllRefClk
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signal Reset : in boolean; -- Reset synchronous to PllRefClk
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signal PhaseCount : inout integer; -- Phase count of Clk with respect to PllRefClk
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ClockCycles : integer) is -- Number of Clk clock cycles in PllRefClk period
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begin
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if rising_edge(Clk) then
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if Reset or PhaseCount = ClockCycles-1 then
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PhaseCount <= 0;
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else
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PhaseCount <= PhaseCount+1;
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end if;
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end if;
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end procedure PhaseCounter;
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procedure CheckExpectedValue(
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signal Clk : in std_logic;
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signal Actual : in std_logic;
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signal Expected : in std_logic;
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Message : string) is
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begin
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if falling_edge(Clk) then
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-- Check if the actual value is as expected.
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assert std_match(Actual, Expected)
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report Message & " not as expected" & LF
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& "Expected = " & std_logic'image(Expected) & LF
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& "Actual = " & std_logic'image(Actual) severity error;
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end if;
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end procedure CheckExpectedValue;
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begin
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ConfigClk <= not ConfigClk after kConfigPer/2 when not StopSim else '0';
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RfClk <= not RfClk after kRfClkPer/2 when not StopSim else '0';
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RfClk2x <= not RfClk2x after kRfClk2xPer/2 when not StopSim else '0';
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DataClk <= not DataClk after kDataClkPer/2 when not StopSim else '0';
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DataClk2x <= not DataClk2x after kDataClk2xPer/2 when not StopSim else '0';
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PllRefClk <= not PllRefClk after kPllRefClkPer/2 when not StopSim else '0';
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-- rAdcEnableData is a constant and is not tested.
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dut: rf_reset_controller
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port map (
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ConfigClk => ConfigClk,
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DataClk => DataClk,
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PllRefClk => PllRefClk,
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RfClk => RfClk,
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RfClk2x => RfClk2x,
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DataClk2x => DataClk2x,
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dAdcResetPulse => dAdcResetPulse,
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dDacResetPulse => dDacResetPulse,
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dAdcDataOutReset_n => dAdcDataOutReset_n,
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r2AdcFirReset_n => r2AdcFirReset_n,
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rAdcRfdcAxiReset_n => rAdcRfdcAxiReset_n,
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rAdcEnableData => open,
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rAdcGearboxReset_n => rAdcGearboxReset_n,
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dDacDataInReset_n => dDacDataInReset_n,
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r2DacFirReset_n => r2DacFirReset_n,
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d2DacFirReset_n => d2DacFirReset_n,
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rDacRfdcAxiReset_n => rDacRfdcAxiReset_n,
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rDacGearboxReset_n => rDacGearboxReset_n,
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cSoftwareControl => cSoftwareControl,
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cSoftwareStatus => cSoftwareStatus
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);
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main: process
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-- Procedure to generate software reset and expected DUR reset output.
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procedure StrobeReset(
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signal TimedReset : out std_logic; -- SW Reset control
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signal ExpectedResetOut : out std_logic; -- Expected reset values
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signal ExpectedAxiResetOut : out std_logic; -- Expected reset values
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signal SwResetStatus : out std_logic; -- Expected SW reset status
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SwReset : integer; -- SW Reset control
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ResetType : std_logic; -- 0 = SW reset, 1 = UHD timed reset
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ResetWait : positive := 1) is -- Wait time for test iteration
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begin
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if ResetType = kSwReset then
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-- Assert software reset control on the rising edge of ConfigClk. Also
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-- change the expected status to don't care as the status will change
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-- only after few ConfigClk period.
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ClkWait(ConfigClk);
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TimedReset <= '0';
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cSoftwareControl(SwReset) <= '1';
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SwResetStatus <= '-';
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ExpectedResetOut <= '-';
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ExpectedAxiResetOut <= '-';
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ClkWait(ConfigClk, 1);
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SwResetStatus <= '0';
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-- Wait for additional ConfigClk before changing the expected reset
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-- value to '0'. This wait is needed to account for pipeline and clock
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-- crossing delays.
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ClkWait(ConfigClk, 1);
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-- Changed expected reset output to '0' (active low).
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ExpectedResetOut <= '0';
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ExpectedAxiResetOut <= '0';
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ClkWait(ConfigClk,1);
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-- SW reset status should be asserted after 3 ConfigClk periods. This
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-- wait is needed to account for pipeline and clock crossings.
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SwResetStatus <= '1';
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-- De-assert software reset
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ClkWait(ConfigClk,2);
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cSoftwareControl(SwReset) <= '0';
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-- Change the expected reset outputs to don't care as it will take few
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-- PllRefClk cycles and ConfigClk to DataClock crossing.
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ExpectedAxiResetOut <= '-';
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ClkWait(ConfigClk,1);
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ExpectedAxiResetOut <= '1';
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-- After few ConfigClk cycles, all reset outputs should be de-asserted.
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ClkWait(ConfigClk,1);
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ExpectedResetOut <= '-';
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ClkWait(ConfigClk,2);
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ExpectedResetOut <= '1';
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-- Wait for ResetWait time before exiting the test iteration.
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ClkWait(ConfigClk,ResetWait);
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else -- Timed command.
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ClkWait(DataClk,ResetWait);
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TimedReset <= '1';
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-- RFDC should not be asserted with timed reset.
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ExpectedAxiResetOut <= '1';
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-- Strobe the reset pulse only for one DataClk period.
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ClkWait(DataClk,1);
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TimedReset <= '0';
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ClkWait(PllRefClk,2);
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ExpectedResetOut <= '-';
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-- Wait for 3 PllRefClk to account for pipeline delays.
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ClkWait(PllRefClk,1);
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ExpectedResetOut <= '0';
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ClkWait(PllRefClk,2);
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ExpectedResetOut <= '-';
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-- Reset should be asserted only for two PllRefClk cycles.
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ClkWait(PllRefClk,2);
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ExpectedResetOut <= '1';
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ClkWait(DataClk,ResetWait); -- Wait between test.
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end if;
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end procedure StrobeReset;
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begin
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-- Expected power on reset values.
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ExpectedAdcReset <= '0';
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ExpectedAxiAdcResetOut <= '0';
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ExpectedDacReset <= '0';
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ExpectedAxiDacResetOut <= '0';
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ClkWait(ConfigClk,1);
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ClkWait(RfClk,1);
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ExpectedAxiAdcResetOut <= '1';
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ExpectedAxiDacResetOut <= '1';
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ClkWait(ConfigClk,1);
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ExpectedAdcReset <= '-';
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ExpectedDacReset <= '-';
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ClkWait(ConfigClk,1);
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ExpectedAdcReset <= '1';
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ExpectedDacReset <= '1';
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ClkWait(ConfigClk,5);
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-- This reset is for simulation to have a common reference to check for
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-- clock alignment.
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ClkWait(PllRefClk,1);
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pReset <= true;
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ClkWait(PllRefClk,1);
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pReset <= false;
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ClkWait(PllRefClk,1);
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---------------------------------------------------------------------------
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-- Test resets from software
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---------------------------------------------------------------------------
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-----------------------------------
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-- ADC
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-----------------------------------
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StrobeReset(dAdcResetPulse, ExpectedAdcReset, ExpectedAxiAdcResetOut,
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ExpectedSwAdcResetDone, kADC_RESET, kSwReset, kResetDoneWait);
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-- Align reset to the rising edge of PllRefClk
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ClkWait(PllRefClk,1);
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StrobeReset(dAdcResetPulse, ExpectedAdcReset, ExpectedAxiAdcResetOut,
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ExpectedSwAdcResetDone, kADC_RESET, kTimedReset, kResetDoneWait);
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StrobeReset(dAdcResetPulse, ExpectedAdcReset, ExpectedAxiAdcResetOut,
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ExpectedSwAdcResetDone, kADC_RESET, kSwReset, kResetDoneWait);
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-- Align reset to the falling edge of PllRefClk.
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ClkWait(PllRefClk,1);
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ClkWait(DataClk,1);
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StrobeReset(dAdcResetPulse, ExpectedAdcReset, ExpectedAxiAdcResetOut,
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ExpectedSwAdcResetDone, kADC_RESET, kTimedReset, kResetDoneWait);
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-----------------------------------
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-- DAC
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-----------------------------------
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StrobeReset(dDacResetPulse, ExpectedDacReset, ExpectedAxiDacResetOut,
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ExpectedSwDacResetDone, kDAC_RESET, kSwReset, kResetDoneWait);
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-- Align reset to the rising edge of PllRefClk.
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ClkWait(PllRefClk,1);
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StrobeReset(dDacResetPulse, ExpectedDacReset, ExpectedAxiDacResetOut,
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ExpectedSwDacResetDone, kDAC_RESET, kTimedReset, kResetDoneWait);
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StrobeReset(dDacResetPulse, ExpectedDacReset, ExpectedAxiDacResetOut,
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ExpectedSwDacResetDone, kDAC_RESET, kSwReset, kResetDoneWait);
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-- Align reset to the falling edge of PllRefClk.
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ClkWait(PllRefClk,1);
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ClkWait(DataClk,1);
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StrobeReset(dDacResetPulse, ExpectedDacReset, ExpectedAxiDacResetOut,
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ExpectedSwDacResetDone, kDAC_RESET, kTimedReset, kResetDoneWait);
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StopSim <= true;
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wait;
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end process main;
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-----------------------------------------------------------------------------
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-- Reset from software and UHD timed command
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-----------------------------------------------------------------------------
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-- Check if the correct resets are getting asserted when UHD timed reset or
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-- software reset is asserted. Except for RFDC AXI-S reset all other resets
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-- should be strobed for UHD timed reset.
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-----------------------------------------------------------------------------
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-- Check if the reset done status is getting asserted as expected.
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CheckExpectedValue(ConfigClk, cSoftwareStatus(kADC_SEQ_DONE),
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ExpectedSwAdcResetDone, "ADC reset done status");
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CheckExpectedValue(ConfigClk, cSoftwareStatus(kDAC_SEQ_DONE),
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ExpectedSwDacResetDone, "DAC reset done status");
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-- Check if resets state in DataClk is as expected.
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CheckExpectedValue(DataClk, dAdcDataOutReset_n, ExpectedAdcReset,
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"ADC data out reset");
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CheckExpectedValue(DataClk, dDacDataInReset_n, ExpectedDacReset,
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"DAC data out reset");
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-- Check if resets state in DataClk2x is as expected.
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CheckExpectedValue(DataClk2x, d2DacFirReset_n, ExpectedDacReset,
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"400M interpolator reset");
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---- Check if resets state in RfClk2x is as expected.
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CheckExpectedValue(RfClk2x, r2AdcFirReset_n, ExpectedAdcReset,
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"ADC re-sampler reset");
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CheckExpectedValue(RfClk2x, r2DacFirReset_n, ExpectedDacReset,
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"DAC re-sampler reset");
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---- Check if resets state in RfClk is as expected.
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CheckExpectedValue(RfClk, rAdcRfdcAxiReset_n, ExpectedAxiAdcResetOut,
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"ADC RFDC AXI-S interface reset");
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CheckExpectedValue(RfClk, rDacRfdcAxiReset_n, ExpectedAxiDacResetOut,
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"DAC RFDC AXI-S interface reset");
|
||||
CheckExpectedValue(RfClk, rAdcGearboxReset_n, ExpectedAdcReset,
|
||||
"ADC gearbox reset");
|
||||
CheckExpectedValue(RfClk, rDacGearboxReset_n, ExpectedDacReset,
|
||||
"DAC gearbox reset");
|
||||
|
||||
|
||||
-----------------------------------------------------------------------------
|
||||
-- Reset alignment checks for resets
|
||||
-----------------------------------------------------------------------------
|
||||
|
||||
-----------------------------------
|
||||
-- Clock counter
|
||||
-----------------------------------
|
||||
-- We use counters to check the phase of all the derived clocks with respect
|
||||
-- to PllRefClk. Each counter will rollover at the rising edge of PllRefClk.
|
||||
-----------------------------------
|
||||
PhaseCounter(DataClk, pReset, dCount, kDataClkCycles);
|
||||
PhaseCounter(DataClk2x, pReset, d2Count, kDataClk2xCycles);
|
||||
PhaseCounter(RfClk, pReset, rCount, kRfClkCycles);
|
||||
PhaseCounter(RfClk2x, pReset, r2Count, kRfClk2xCycles);
|
||||
|
||||
-- Check for DataClk based synchronous reset alignment to PllRefClk.
|
||||
CheckAlignment(DataClk, dAdcDataOutReset_n, dAdcDataOutResetDlyd_n, dCount,
|
||||
"ADC data out");
|
||||
CheckAlignment(DataClk, dDacDataInReset_n, dDacDataInResetDlyd_n, dCount,
|
||||
"DAC data in");
|
||||
|
||||
-- Check for DataClk2x based synchronous reset alignment to PllRefClk.
|
||||
CheckAlignment(DataClk2x, d2DacFirReset_n, d2DacFirResetDlyd_n, d2Count,
|
||||
"400M DAC FIR Filter");
|
||||
|
||||
-- Check for RfClk based synchronous reset alignment to PllRefClk.
|
||||
CheckAlignment(RfClk, rAdcRfdcAxiReset_n, rAdcRfdcAxiResetDlyd_n, rCount,
|
||||
"ADC RFDC reset ");
|
||||
CheckAlignment(RfClk, rDacRfdcAxiReset_n, rDacRfdcAxiResetDlyd_n, rCount,
|
||||
"DAC RFDC reset ");
|
||||
|
||||
-- Check for RfClk2x based synchronous reset alignment to PllRefClk.
|
||||
CheckAlignment(RfClk2x, r2AdcFirReset_n, r2AdcFirResetDlyd_n, r2Count,
|
||||
"ADC decimation filter reset ");
|
||||
CheckAlignment(RfClk2x, r2DacFirReset_n, r2DacFirResetDlyd_n, r2Count,
|
||||
"DAC interpolation filter reset ");
|
||||
|
||||
end RTL;
|
||||
Reference in New Issue
Block a user