fpga: x400: Add support for X410 motherboard FPGA

Co-authored-by: Andrew Moch <Andrew.Moch@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com>
Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com>
Co-authored-by: Max Köhler <max.koehler@ni.com>
Co-authored-by: Michael Auchter <michael.auchter@ni.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>
Co-authored-by: Hector Rubio <hrubio@ni.com>


Original-commit: 6d3765605262016a80f71e36357f749ea35cbe5a

top/x400/rf/common/sync_wrapper.v

@@ -0,0 +1,43 @@
+//
+// Copyright 2021 Ettus Research, a National Instruments Brand
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: sync_wrapper
+//
+// Description:
+//
+//   As the original synchronizer component has port signal names that are
+//   incompatible with VHDL (in, out), this modules provides an an interface to
+//   instantiate the synchronizer block in VHDL.
+//
+
+`default_nettype none
+
+module sync_wrapper #(
+   parameter WIDTH            = 1,
+   parameter STAGES           = 2,
+   parameter INITIAL_VAL      = 0,
+   parameter FALSE_PATH_TO_IN = 1
+)(
+   input  wire             clk,
+   input  wire             rst,
+   input  wire [WIDTH-1:0] signal_in,
+   output wire [WIDTH-1:0] signal_out
+);
+
+synchronizer #(
+  .WIDTH             (WIDTH),
+  .STAGES            (STAGES),
+  .INITIAL_VAL       (INITIAL_VAL),
+  .FALSE_PATH_TO_IN  (FALSE_PATH_TO_IN)
+) synchronizer_i (
+  .clk  (clk),
+  .rst  (rst),
+  .in   (signal_in),
+  .out  (signal_out)
+);
+
+endmodule //sync_wrapper
+
+`default_nettype wire