fpga: x400: Add support for X410 motherboard FPGA
Co-authored-by: Andrew Moch <Andrew.Moch@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Michael Auchter <michael.auchter@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Hector Rubio <hrubio@ni.com> Original-commit: 6d3765605262016a80f71e36357f749ea35cbe5a
This commit is contained in:
Wade Fife
committed by
Aaron Rossetto
Aaron Rossetto
co-authored by
Andrew Moch
Daniel Jepson
Javier Valenzuela
Joerg Hofrichter
Kumaran Subramoniam
Max Köhler
Michael Auchter
Paul Butler
Hector Rubio
Andrew Moch
Daniel Jepson
Javier Valenzuela
Joerg Hofrichter
Kumaran Subramoniam
Max Köhler
Michael Auchter
Paul Butler
Hector Rubio
parent
bfef20ea45
commit
61782b02d7
@@ -0,0 +1,216 @@
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--
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-- Copyright 2021 Ettus Research, a National Instruments Brand
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--
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-- SPDX-License-Identifier: LGPL-3.0-or-later
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--
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-- Module: rf_reset
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--
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-- Description:
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--
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-- Control RFDC, ADC, and DAC resets.
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--
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity rf_reset is
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port(
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-- Clocks used in the data path.
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DataClk : in std_logic;
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PllRefClk : in std_logic;
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RfClk : in std_logic;
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RfClk2x : in std_logic;
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DataClk2x : in std_logic;
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-- Master resets from the Radio.
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dTimedReset : in std_logic;
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dSwReset : in std_logic;
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-- Resets outputs.
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dReset_n : out std_logic := '0';
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d2Reset_n : out std_logic := '0';
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r2Reset_n : out std_logic := '0';
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rAxiReset_n : out std_logic := '0';
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rReset_n : out std_logic := '0'
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);
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end rf_reset;
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architecture RTL of rf_reset is
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-- POR value for all resets are active high or low.
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signal dResetPulseDly : std_logic_vector(2 downto 0) := "111";
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signal dResetPulseStretch : std_logic := '1';
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signal pResetPulseStretch : std_logic_vector(1 downto 0) := "11";
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signal pResetPulse_n : std_logic := '0';
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signal pAxiReset_n : std_logic := '0';
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begin
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-----------------------------------------------------------------------------
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-- Clock Phase Diagram
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-----------------------------------------------------------------------------
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-- Before we look into the details of the clock alignment, here is the clock
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-- frequencies of all the synchronous clocks that is used in the design.
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-- PllRefClk is the reference clock for the FPGA PLL and all other clocks are
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-- derived from PllRefClk. PllRefClk for X410 is ~62.5 MHz
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-- PllRefClk = ~62.5 MHz (Sample clock/48. This is the X410 configuration and
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-- could be different for other x4xx variants.)
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-- DataClk = PllRefClk*2
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-- DataClkx2 = PllRefClk*4
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-- RfClk = PllRefClk*3
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-- RfClkx2 = PllRefClk*6
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-- DataClk = PllRefClk*4 for legacy mode. In legacy mode, we will not use
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-- DataClkx2 as the clock frequency will be too high to close timing.
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-- Five clocks with five different frequencies, all related and occasionally
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-- aligned. Rising edge of all clocks are aligned to the rising edge of
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-- PllRefClk. We will use the rising edge of PllRefClk as the reference to
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-- assert synchronous reset for all clock domains. The synchronous reset
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-- pulse is in the DataClk domain. As we can see from the timing diagram, the
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-- DataClk rising edge is not always aligned to the rising edge of all the
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-- other clocks. But, it is guaranteed that the DataClk will be aligned to
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-- all the other clock on the rising edge of PLL reference clock. In case 1,
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-- the synchronous reset pulse is on the DataClk edge where the data clock is
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-- not aligned to RfClk. We stretch the pulse from DataClk domain and send
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-- the reset out on the rising edge of PllRefClk where all the clocks rising
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-- edge is aligned. In case 2, the synchronous reset is received on the
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-- DataClk cycle where all the clocks are aligned. This is because, in
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-- case 2, the synchronous reset is received on the rising edge of PllRefClk.
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-- For case 1 and case 2, all the output resets are asserted only on the
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-- PllRefClk rising edge to guarantee a known relationship between the resets
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-- in different clock domains.
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--
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-- Alignment * * *
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-- ___________ ___________ ___________ ___________ ___________
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-- PllRefClk __| |___________| |___________| |___________| |___________| |
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-- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
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-- RfClk2x __| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_
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-- ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___
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-- RfClk __| |___| |___| |___| |___| |___| |___| |___| |___| |___| |___| |___| |___| |___|
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-- __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __
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-- DataClk2x __| |__| |__| |__| |__| |__| |__| |__| |__| |__| |__| |__| |__| |__| |__| |__| |__| |__| |__|
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-- _____ _____ _____ _____ _____ _____ _____ _____ _____
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-- DataClk __| |_____| |_____| |_____| |_____| |_____| |_____| |_____| |_____| |_____|
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-- . : : : :
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-- --------- Case 1 ---------.-- : : : :
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-- ^ : : ^ :
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-- Reset Strobe --> | : Aligned reset strobe -->| :
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-- ____________ : : : :
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-- dResetPulse________| |______________________________________ : :
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-- : _____________________________________________________________________________
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-- dResetPulseStretch ______________________| :
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-- : ________________________________________________
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-- pResetPulseStretch ____________________________________________| : : |___
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-- _________________________________________________________________________ :
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-- pResetPulse_n : |________________________________
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-- : : : :
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-- --------- Case 2 ----------- : : : :
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-- ^ : ^ :
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-- Reset Strobe --> | : | <-- Aligned reset strobe
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-- ____________ : : :
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-- dResetPulse(0) ________| |______________________________________________________________________________
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-- _______________________________________________________________________________
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-- dResetPulseStretch ______________________| :
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-- ________________________________________________________
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-- pResetPulseStretch ____________________________________________| :
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-- _________________________________________________________________________
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-- pResetPulse_n |________________________________
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-- --------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Implementation
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-----------------------------------------------------------------------------
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-- Since the dTimedReset is asserted only for one DataClk cycle, we need to
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-- stretch the strobe to four DataClk cycles, so the strobe is wide enough to
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-- be sampled by PllRefClk which is four times the DataClk period. Pulse
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-- stretch is done for 4 DataClk periods to support the legacy mode. We also
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-- do a logical OR on resets from software. Software resets are from the
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-- ConfigClock domain which is a slower clock than the PllRefClk. So, we
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-- don't have to stretch the software reset.
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PulseStretch: process(DataClk)
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begin
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if rising_edge(DataClk) then
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dResetPulseDly <= dResetPulseDly(1 downto 0) & (dTimedReset or dSwReset);
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dResetPulseStretch <= '0';
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if (dResetPulseDly /= "000") or dTimedReset = '1' or dSwReset = '1' then
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dResetPulseStretch <= '1';
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end if;
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end if;
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end process PulseStretch;
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-- Strobe reset pulse for 2 PllRefClk period to make sure we have the reset
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-- asserted for longer period. The FIR filter is the only design that
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-- requires reset to be asserted for 2 clock cycles. This requirement is
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-- satisfied with one PllRefClk period. RFDC does not have any AXI stream
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-- reset time requirement. We will reset all designs for two PllRefClk period
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-- just to be on the safer side. The same strategy is used for DAC resets as
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-- well.
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ResetOut: process(PllRefClk)
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begin
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if rising_edge(PllRefClk) then
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pResetPulseStretch <= pResetPulseStretch(0) & dResetPulseStretch;
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pResetPulse_n <= not (pResetPulseStretch(1) or pResetPulseStretch(0));
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end if;
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end process ResetOut;
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-- We are using PllRefClk as the reference and issuing resets to all the
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-- other clock domains. We are not trying to align all the resets in
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-- different clock domains. We are making sure that all resets will be
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-- asserted with respect to each other at the same time from run to run.
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DataClkReset: process(DataClk)
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begin
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if rising_edge(DataClk) then
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dReset_n <= pResetPulse_n;
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end if;
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end process DataClkReset;
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DataClk2xReset: process(DataClk2x)
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begin
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if rising_edge(DataClk2x) then
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d2Reset_n <= pResetPulse_n;
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end if;
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end process DataClk2xReset;
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Rfclk2xReset: process(RfClk2x)
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begin
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if rising_edge(RfClk2x) then
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r2Reset_n <= pResetPulse_n;
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end if;
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end process Rfclk2xReset;
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RfclkReset: process(RfClk)
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begin
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if rising_edge(RfClk) then
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rReset_n <= pResetPulse_n;
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end if;
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end process RfclkReset;
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-------------------------------------
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-- RF Resets
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-------------------------------------
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-- RFDC resets are asserted only once and it should be done using the reset
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-- from software. This is because we want the RFDC AXI-S interface in reset
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-- until the RfClk is stable. The only way to know if the RfClk is stable is
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-- by reading the lock status of sample clock PLL and MMCM used to generate
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-- all clocks in the signal path. dSwReset is a software reset while is
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-- asserted for a longer period of time and it does not require any pulse
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-- stretch.
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RfdcReset: process(PllRefClk)
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begin
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if rising_edge(PllRefClk) then
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pAxiReset_n <= not dSwReset;
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end if;
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end process RfdcReset;
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RfclkAxiReset: process(RfClk)
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begin
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if rising_edge(RfClk) then
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rAxiReset_n <= pAxiReset_n;
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end if;
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end process RfclkAxiReset;
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end RTL;
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