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fpga: x400: Add support for X410 motherboard FPGA

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Co-authored-by: Andrew Moch <Andrew.Moch@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com>
Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com>
Co-authored-by: Max Köhler <max.koehler@ni.com>
Co-authored-by: Michael Auchter <michael.auchter@ni.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>
Co-authored-by: Hector Rubio <hrubio@ni.com>


Original-commit: 6d3765605262016a80f71e36357f749ea35cbe5a
This commit is contained in:
Wade Fife
2021-06-10 11:56:58 -05:00
committed by Aaron Rossetto
co-authored by Andrew Moch Daniel Jepson Javier Valenzuela Joerg Hofrichter Kumaran Subramoniam Max Köhler Michael Auchter Paul Butler Hector Rubio
parent bfef20ea45
commit 61782b02d7
205 changed files with 299634 additions and 0 deletions
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top/x400/regmap/rfdc_timing_regmap_utils.vh
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//
// Copyright 2021 Ettus Research, A National Instruments Company
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: rfdc_timing_regmap_utils.vh
// Description:
// The constants in this file are autogenerated by XmlParse.
//===============================================================================
// A numerically ordered list of registers and their HDL source files
//===============================================================================
// NCO_RESET_REG : 0x0 (rfdc_timing_control.v)
// GEARBOX_RESET_REG : 0x4 (rfdc_timing_control.v)
//===============================================================================
// RegTypes
//===============================================================================
//===============================================================================
// Register Group RFDC_TIMING_REGS
//===============================================================================
// NCO_RESET_REG Register (from rfdc_timing_control.v)
localparam NCO_RESET_REG = 'h0; // Register Offset
localparam NCO_RESET_REG_SIZE = 32; // register width in bits
localparam NCO_RESET_REG_MASK = 32'h3;
localparam NCO_RESET_START_SIZE = 1; //NCO_RESET_REG:NCO_RESET_START
localparam NCO_RESET_START_MSB = 0; //NCO_RESET_REG:NCO_RESET_START
localparam NCO_RESET_START = 0; //NCO_RESET_REG:NCO_RESET_START
localparam NCO_RESET_DONE_SIZE = 1; //NCO_RESET_REG:NCO_RESET_DONE
localparam NCO_RESET_DONE_MSB = 1; //NCO_RESET_REG:NCO_RESET_DONE
localparam NCO_RESET_DONE = 1; //NCO_RESET_REG:NCO_RESET_DONE
// GEARBOX_RESET_REG Register (from rfdc_timing_control.v)
localparam GEARBOX_RESET_REG = 'h4; // Register Offset
localparam GEARBOX_RESET_REG_SIZE = 32; // register width in bits
localparam GEARBOX_RESET_REG_MASK = 32'h3;
localparam ADC_RESET_SIZE = 1; //GEARBOX_RESET_REG:ADC_RESET
localparam ADC_RESET_MSB = 0; //GEARBOX_RESET_REG:ADC_RESET
localparam ADC_RESET = 0; //GEARBOX_RESET_REG:ADC_RESET
localparam DAC_RESET_SIZE = 1; //GEARBOX_RESET_REG:DAC_RESET
localparam DAC_RESET_MSB = 1; //GEARBOX_RESET_REG:DAC_RESET
localparam DAC_RESET = 1; //GEARBOX_RESET_REG:DAC_RESET