fpga: x400: Add support for X410 motherboard FPGA

Co-authored-by: Andrew Moch <Andrew.Moch@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Michael Auchter <michael.auchter@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Hector Rubio <hrubio@ni.com> Original-commit: 6d3765605262016a80f71e36357f749ea35cbe5a
2021-06-10 11:56:58 -05:00
parent bfef20ea45
commit 61782b02d7
205 changed files with 299634 additions and 0 deletions
@@ -0,0 +1,110 @@
+//
+// Copyright 2021 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: axi_hpm0_regmap_utils.vh
+// Description:
+// The constants in this file are autogenerated by XmlParse.
+
+//===============================================================================
+// A numerically ordered list of registers and their HDL source files
+//===============================================================================
+
+  // RPU          : 0x80000000 (common_regs.v)
+  // JTAG_ENGINE  : 0x1000000000 (common_regs.v)
+  // WR           : 0x100003F000 (common_regs.v)
+  // MPM_ENDPOINT : 0x1000080000 (common_regs.v)
+  // CORE_REGS    : 0x10000A0000 (common_regs.v)
+  // INT_ETH_DMA  : 0x10000A4000 (common_regs.v)
+  // INT_ETH_REGS : 0x10000AA000 (common_regs.v)
+  // RFDC         : 0x1000100000 (common_regs.v)
+  // RFDC_REGS    : 0x1000140000 (common_regs.v)
+  // QSFP_0_0     : 0x1200000000 (uhd_regs.v)
+  // QSFP_0_1     : 0x1200010000 (uhd_regs.v)
+  // QSFP_0_2     : 0x1200020000 (uhd_regs.v)
+  // QSFP_0_3     : 0x1200030000 (uhd_regs.v)
+  // QSFP_1_0     : 0x1200040000 (uhd_regs.v)
+  // QSFP_1_1     : 0x1200050000 (uhd_regs.v)
+  // QSFP_1_2     : 0x1200060000 (uhd_regs.v)
+  // QSFP_1_3     : 0x1200070000 (uhd_regs.v)
+
+//===============================================================================
+// RegTypes
+//===============================================================================
+
+//===============================================================================
+// Register Group COMMON
+//===============================================================================
+
+  // RPU Window (from common_regs.v)
+  localparam RPU = 'h80000000; // Window Offset
+  localparam RPU_SIZE = 'h10000;  // size in bytes
+
+  // JTAG_ENGINE Window (from common_regs.v)
+  localparam JTAG_ENGINE = 'h1000000000; // Window Offset
+  localparam JTAG_ENGINE_SIZE = 'h1000;  // size in bytes
+
+  // WR Window (from common_regs.v)
+  localparam WR = 'h100003F000; // Window Offset
+  localparam WR_SIZE = 'h1000;  // size in bytes
+
+  // MPM_ENDPOINT Window (from common_regs.v)
+  localparam MPM_ENDPOINT = 'h1000080000; // Window Offset
+  localparam MPM_ENDPOINT_SIZE = 'h20000;  // size in bytes
+
+  // CORE_REGS Window (from common_regs.v)
+  localparam CORE_REGS = 'h10000A0000; // Window Offset
+  localparam CORE_REGS_SIZE = 'h4000;  // size in bytes
+
+  // INT_ETH_DMA Window (from common_regs.v)
+  localparam INT_ETH_DMA = 'h10000A4000; // Window Offset
+  localparam INT_ETH_DMA_SIZE = 'h6000;  // size in bytes
+
+  // INT_ETH_REGS Window (from common_regs.v)
+  localparam INT_ETH_REGS = 'h10000AA000; // Window Offset
+  localparam INT_ETH_REGS_SIZE = 'h2000;  // size in bytes
+
+  // RFDC Window (from common_regs.v)
+  localparam RFDC = 'h1000100000; // Window Offset
+  localparam RFDC_SIZE = 'h40000;  // size in bytes
+
+  // RFDC_REGS Window (from common_regs.v)
+  localparam RFDC_REGS = 'h1000140000; // Window Offset
+  localparam RFDC_REGS_SIZE = 'h20000;  // size in bytes
+
+//===============================================================================
+// Register Group UHD_ONLY
+//===============================================================================
+
+  // QSFP_0_0 Window (from uhd_regs.v)
+  localparam QSFP_0_0 = 'h1200000000; // Window Offset
+  localparam QSFP_0_0_SIZE = 'h10000;  // size in bytes
+
+  // QSFP_0_1 Window (from uhd_regs.v)
+  localparam QSFP_0_1 = 'h1200010000; // Window Offset
+  localparam QSFP_0_1_SIZE = 'h10000;  // size in bytes
+
+  // QSFP_0_2 Window (from uhd_regs.v)
+  localparam QSFP_0_2 = 'h1200020000; // Window Offset
+  localparam QSFP_0_2_SIZE = 'h10000;  // size in bytes
+
+  // QSFP_0_3 Window (from uhd_regs.v)
+  localparam QSFP_0_3 = 'h1200030000; // Window Offset
+  localparam QSFP_0_3_SIZE = 'h10000;  // size in bytes
+
+  // QSFP_1_0 Window (from uhd_regs.v)
+  localparam QSFP_1_0 = 'h1200040000; // Window Offset
+  localparam QSFP_1_0_SIZE = 'h10000;  // size in bytes
+
+  // QSFP_1_1 Window (from uhd_regs.v)
+  localparam QSFP_1_1 = 'h1200050000; // Window Offset
+  localparam QSFP_1_1_SIZE = 'h10000;  // size in bytes
+
+  // QSFP_1_2 Window (from uhd_regs.v)
+  localparam QSFP_1_2 = 'h1200060000; // Window Offset
+  localparam QSFP_1_2_SIZE = 'h10000;  // size in bytes
+
+  // QSFP_1_3 Window (from uhd_regs.v)
+  localparam QSFP_1_3 = 'h1200070000; // Window Offset
+  localparam QSFP_1_3_SIZE = 'h10000;  // size in bytes