fpga: x400: Add support for X410 motherboard FPGA
Co-authored-by: Andrew Moch <Andrew.Moch@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Michael Auchter <michael.auchter@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Hector Rubio <hrubio@ni.com> Original-commit: 6d3765605262016a80f71e36357f749ea35cbe5a
This commit is contained in:
Wade Fife
committed by
Aaron Rossetto
Aaron Rossetto
co-authored by
Andrew Moch
Daniel Jepson
Javier Valenzuela
Joerg Hofrichter
Kumaran Subramoniam
Max Köhler
Michael Auchter
Paul Butler
Hector Rubio
Andrew Moch
Daniel Jepson
Javier Valenzuela
Joerg Hofrichter
Kumaran Subramoniam
Max Köhler
Michael Auchter
Paul Butler
Hector Rubio
parent
bfef20ea45
commit
61782b02d7
@@ -0,0 +1,173 @@
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//
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// Copyright 2021 Ettus Research, A National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: eth_10g
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//
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// Description: Wrapper for the 10G mac and phy
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module eth_10g (
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// Resets
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input logic areset,
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// Clock for misc stuff
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input logic clk100,
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// Shared Quad signals
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output logic[0:0] qpll0_reset,
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input logic[0:0] qpll0_lock,
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input logic[0:0] qpll0_clk,
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input logic[0:0] qpll0_refclk,
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output logic[0:0] qpll1_reset,
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input logic[0:0] qpll1_lock,
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input logic[0:0] qpll1_clk,
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input logic[0:0] qpll1_refclk,
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// RX Clk for output
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output logic rx_rec_clk_out,
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// MGT high-speed IO
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output logic tx_p,
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output logic tx_n,
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input logic rx_p,
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input logic rx_n,
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// Data port
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output logic mgt_clk,
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output logic mgt_rst,
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// Interface clocks for mgt_tx and mgt_rx are NOT used (logic uses using mgt_clk)
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AxiStreamIf.slave mgt_tx,
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AxiStreamIf.master mgt_rx,
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// Axi port
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AxiLiteIf.slave mgt_axil,
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// Misc
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output logic [31:0] phy_status,
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input logic [31:0] mac_ctrl,
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output logic [31:0] mac_status,
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output logic phy_reset,
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output logic link_up
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);
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import PkgAxiLite::*;
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assign phy_status[31:8] = 24'h0;
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assign mac_status[31:9] = 23'h0;
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assign link_up = phy_status[0];
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// respond with error if anyone reads this memory region
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always_comb begin
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mgt_axil.awready = 1'b1;
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mgt_axil.wready = 1'b1;
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mgt_axil.bresp= SLVERR;
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mgt_axil.bvalid = 1'b1;
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mgt_axil.arready = 1'b1;
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mgt_axil.rdata = 'b0;
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mgt_axil.rresp = SLVERR;
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mgt_axil.rvalid = 1'b1;
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end
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logic xgmii_clk;
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logic [63:0] xgmii_txd;
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logic [7:0] xgmii_txc;
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logic [63:0] xgmii_rxd;
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logic [7:0] xgmii_rxc;
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logic xge_phy_resetdone;
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assign phy_reset = !xge_phy_resetdone;
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assign mgt_clk = xgmii_clk;
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// This is a heavily replicated signal, add some pipeline
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// to it to make it easier to spread out
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logic mgt_rst_0;
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always_ff @(posedge mgt_clk,posedge areset) begin : reset_timing_dff
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if (areset) begin
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mgt_rst_0 = 1'b1;
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mgt_rst = 1'b1;
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end else begin
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mgt_rst_0 = !link_up;
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mgt_rst = mgt_rst_0;
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end
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end
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// areset pin notes - reset is used asynchronously
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ten_gige_phy ten_gige_phy_i (
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.areset (areset),
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.dclk (clk100),
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.xgmii_clk (xgmii_clk),
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.txp (tx_p),
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.txn (tx_n),
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.rxp (rx_p),
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.rxn (rx_n),
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.xgmii_txd (xgmii_txd),
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.xgmii_txc (xgmii_txc),
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.xgmii_rxd (xgmii_rxd),
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.xgmii_rxc (xgmii_rxc),
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.qpll0_refclk (qpll0_refclk),
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.qpll0_clk (qpll0_clk),
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.qpll0_lock (qpll0_lock),
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.qpll0_reset (qpll0_reset),
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.qpll1_refclk (qpll1_refclk),
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.qpll1_clk (qpll1_clk),
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.qpll1_lock (qpll1_lock),
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.qpll1_reset (qpll1_reset),
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.rxrecclkout (rx_rec_clk_out),
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.core_status (phy_status[7:0]),
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.reset_done (xge_phy_resetdone)
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);
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xge_mac_wrapper #(
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.PORTNUM(0),
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.WISHBONE(0),
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.ADD_PREAMBLE(0),
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.CROSS_TO_SYSCLK(0),
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.CUT_THROUGH(15)
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) xge_mac_wrapper_i (
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// XGMII
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.xgmii_clk(xgmii_clk),
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.xgmii_txd(xgmii_txd),
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.xgmii_txc(xgmii_txc),
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.xgmii_rxd(xgmii_rxd),
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.xgmii_rxc(xgmii_rxc),
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// Client FIFO Interfaces
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.sys_clk(1'b0),
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.sys_rst(1'b0),
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.rx_tdata(mgt_rx.tdata),
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.rx_tuser(mgt_rx.tuser),
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.rx_tlast(mgt_rx.tlast),
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.rx_tvalid(mgt_rx.tvalid),
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.rx_tready(mgt_rx.tready),
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.tx_tdata(mgt_tx.tdata),
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.tx_tuser(mgt_tx.tuser), // Bit[3] (error) is ignored for now.
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.tx_tlast(mgt_tx.tlast),
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.tx_tvalid(mgt_tx.tvalid),
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.tx_tready(mgt_tx.tready),
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// Control and Status
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.phy_ready(xge_phy_resetdone),
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.ctrl_tx_enable(mac_ctrl[0]),
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.status_crc_error(mac_status[0]),
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.status_fragment_error(mac_status[1]),
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.status_txdfifo_ovflow(mac_status[2]),
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.status_txdfifo_udflow(mac_status[3]),
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.status_rxdfifo_ovflow(mac_status[4]),
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.status_rxdfifo_udflow(mac_status[5]),
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.status_pause_frame_rx(mac_status[6]),
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.status_local_fault(mac_status[7]),
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.status_remote_fault(mac_status[8]),
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// MDIO
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.mdc(),
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.mdio_in(),
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.mdio_out(1'b0),
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// Wishbone
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.wb_ack_o(),
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.wb_dat_o(),
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.wb_adr_i(8'b0),
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.wb_clk_i(1'b0),
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.wb_cyc_i(1'b0),
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.wb_dat_i(32'b0),
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.wb_rst_i(1'b0),
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.wb_stb_i(1'b0),
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.wb_we_i (1'b0),
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.wb_int_o()
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);
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endmodule
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