fpga: x400: Add support for X410 motherboard FPGA
Co-authored-by: Andrew Moch <Andrew.Moch@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Michael Auchter <michael.auchter@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Hector Rubio <hrubio@ni.com> Original-commit: 6d3765605262016a80f71e36357f749ea35cbe5a
This commit is contained in:
Wade Fife
committed by
Aaron Rossetto
Aaron Rossetto
co-authored by
Andrew Moch
Daniel Jepson
Javier Valenzuela
Joerg Hofrichter
Kumaran Subramoniam
Max Köhler
Michael Auchter
Paul Butler
Hector Rubio
Andrew Moch
Daniel Jepson
Javier Valenzuela
Joerg Hofrichter
Kumaran Subramoniam
Max Köhler
Michael Auchter
Paul Butler
Hector Rubio
parent
bfef20ea45
commit
61782b02d7
@@ -0,0 +1,62 @@
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#
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# Copyright 2021 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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#-------------------------------------------------
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# Top-of-Makefile
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#-------------------------------------------------
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# Define BASE_DIR to point to the "top" dir
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BASE_DIR = $(abspath ../../../../../top)
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# Include viv_sim_preamble after defining BASE_DIR
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include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
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#-------------------------------------------------
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# Design Specific
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#-------------------------------------------------
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# Include makefiles and sources for the DUT and its dependencies
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include $(BASE_DIR)/../lib/axi4s_sv/Makefile.srcs
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include $(BASE_DIR)/../lib/fifo/Makefile.srcs
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# If you generate the Xilinx CORE with an AXI interface you can find Xilinx's LBUS translators here
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#$(abspath ../../../build-ip/xczu28drffvg1517-1e/eth_100g_bd/eth_100g_bd/ip/eth_100g_bd_cmac_usplus_0_0/eth_100g_bd_cmac_usplus_0_0/example_design/eth_100g_bd_cmac_usplus_0_0_lbus2axis_segmented_top.v) \
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#$(abspath ../../../build-ip/xczu28drffvg1517-1e/eth_100g_bd/eth_100g_bd/ip/eth_100g_bd_cmac_usplus_0_0/eth_100g_bd_cmac_usplus_0_0/example_design/eth_100g_bd_cmac_usplus_0_0_axis2lbus_segmented_top.v) \
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DESIGN_SRCS = $(abspath \
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$(abspath ../eth_100g_axis2lbus.sv) \
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$(abspath ../eth_100g_lbus2axis.sv) \
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$(FIFO_SRCS) \
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$(AXI4S_SV_SRCS) \
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)
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#-------------------------------------------------
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# Testbench Specific
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#-------------------------------------------------
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MODELSIM_LIBS += secureip unimacro_ver unisims_ver xilinx_vip xpm fifo_generator_v13_2_4
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MODELSIM_ARGS += glbl -t 1fs
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# Define toplevel module
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TB_TOP_MODULE ?= lbus_all_tb
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SIM_TOP = $(TB_TOP_MODULE)
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SIM_SRCS = \
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$(abspath ../PkgEth100gLbus.sv) \
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$(abspath axi_lbus_tb.sv) \
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$(abspath lbus_axi_tb.sv) \
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$(abspath $(TB_TOP_MODULE).sv) \
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$(VIVADO_PATH)/data/verilog/src/glbl.v \
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# Suppressing the following worthless reminder.
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#* Warning: M:/usrp4-hw/oss-repo/fpga/usrp3/lib/axi4s_sv/axi4s_remove_bytes.sv(228): (vlog-2583) [SVCHK] -
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# Extra checking for conflicts with always_comb and always_latch variables is done at vopt time
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SVLOG_ARGS = -suppress 2583 -keep_delta
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VLOG_ARGS = -keep_delta
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#-------------------------------------------------
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# Bottom-of-Makefile
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#-------------------------------------------------
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# Include all simulator specific makefiles here
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# Each should define a unique target to simulate
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# e.g. xsim, vsim, etc and a common "clean" target
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include $(BASE_DIR)/../tools/make/viv_simulator.mak
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@@ -0,0 +1,285 @@
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//
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// Copyright 2021 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: axi_lbus_tb
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//
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// Description:
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//
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// Testbench for eth_interface
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//
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module axi_lbus_tb #(
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parameter TEST_NAME = ""
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)(
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/* no IO */
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);
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// Include macros and time declarations for use with PkgTestExec
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`define TEST_EXEC_OBJ test
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`include "test_exec.svh"
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import PkgAxiStreamBfm::*;
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import PkgEthernet::*;
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import PkgTestExec::*;
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import PkgEth100gLbus::*;
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localparam DATA_WIDTH = 512;
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localparam USER_WIDTH = $clog2(DATA_WIDTH/8)+1;
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localparam NUM_SEG = 4;
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localparam SEG_DATA_WIDTH = DATA_WIDTH/NUM_SEG;
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localparam SEG_BYTES = SEG_DATA_WIDTH/8;
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//----------------------------------------------------
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// clocks
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//----------------------------------------------------
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logic clk;
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logic rst;
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sim_clock_gen #(.PERIOD(5), .AUTOSTART(1))
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clk_gen (.clk(clk), .rst(rst));
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//----------------------------------------------------
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//interfaces
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//----------------------------------------------------
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AxiStreamIf #(.DATA_WIDTH(DATA_WIDTH),.USER_WIDTH(USER_WIDTH))
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axis (clk, rst);
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//----------------------------------------------------
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// DUT
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//----------------------------------------------------
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lbus_t lbus_out [NUM_SEG-1:0];
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lbus_t lbus_g [NUM_SEG-1:0];
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logic lbus_rdy = 1;
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eth_100g_axi2lbus #(.FIFO_DEPTH(5),.NUM_SEG(NUM_SEG)) DUT (
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.axis(axis),
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.lbus_rdy(lbus_rdy),
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.lbus_out(lbus_out)
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);
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//----------------------------------------------------
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// Xilinx golden model
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// When Xilinx is generated with an AXI interface xilinx prints
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// an axi2lbus converter that has trouble meeting timing
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// this is preserved to allow comparison to that
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// TODO: remove when timing is passing and refactor is done
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//----------------------------------------------------
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/*
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eth_100g_bd_cmac_usplus_0_0_axis2lbus_segmented_top GOLD (
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.core_clk(clk),
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.core_rst(rst),
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// AXIS IF
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.axis_tvalid(axis.tvalid),
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.axis_tready(),
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.axis_tdata(axis.tdata),
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.axis_tlast(axis.tlast),
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.axis_tkeep(axis.tkeep),
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.axis_tuser(1'b0),
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// LBUS IF
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.lbus_rdyout(lbus_rdy),
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.lbus_ovfout(1'b0),
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.lbus_unfout(1'b0),
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// Segment 0
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.lbus_ena0(lbus_g[0].ena),
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.lbus_data0(lbus_g[0].data),
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.lbus_sop0(lbus_g[0].sop),
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.lbus_eop0(lbus_g[0].eop),
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.lbus_mty0(lbus_g[0].mty),
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.lbus_err0(lbus_g[0].err),
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// Segment 1
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.lbus_ena1(lbus_g[1].ena),
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.lbus_data1(lbus_g[1].data),
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.lbus_sop1(lbus_g[1].sop),
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.lbus_eop1(lbus_g[1].eop),
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.lbus_mty1(lbus_g[1].mty),
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.lbus_err1(lbus_g[1].err),
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// Segment 2
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.lbus_ena2(lbus_g[2].ena),
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.lbus_data2(lbus_g[2].data),
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.lbus_sop2(lbus_g[2].sop),
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.lbus_eop2(lbus_g[2].eop),
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.lbus_mty2(lbus_g[2].mty),
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.lbus_err2(lbus_g[2].err),
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// Segment 3
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.lbus_ena3(lbus_g[3].ena),
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.lbus_data3(lbus_g[3].data),
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.lbus_sop3(lbus_g[3].sop),
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.lbus_eop3(lbus_g[3].eop),
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.lbus_mty3(lbus_g[3].mty),
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.lbus_err3(lbus_g[3].err)
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);
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*/
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//----------------------------------------------------
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//BFMS
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//----------------------------------------------------
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TestExec test = new();
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AxiStreamBfm #(.DATA_WIDTH(DATA_WIDTH),.USER_WIDTH(USER_WIDTH)) axi =
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new(.slave(null),.master(axis));
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//---------------------------------------------------------------------------
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// Tests
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//---------------------------------------------------------------------------
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// use Test timeout to check reset goes away
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task test_reset();
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test.start_test({TEST_NAME,"Wait for Reset"}, 10us);
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wait(!rst);
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repeat (10) @(posedge clk);
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test.end_test();
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endtask : test_reset
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typedef AxiStreamPacket #(DATA_WIDTH,USER_WIDTH) AxisPacket_t;
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typedef XportStreamPacket #(DATA_WIDTH) XportPacket_t;
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task automatic check_lbus(AxisPacket_t packets[$]);
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int idle_insert = 0;
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int byte_count = 0;
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int first_clk = 1;
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// loop over packets
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foreach(packets[i]) begin
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automatic raw_pkt_t pay;
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pay = packets[i].dump_bytes;
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first_clk=1;
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while (pay.size() > 0) begin
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@(posedge clk);
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if (lbus_rdy) begin
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if (lbus_out[0].ena) begin
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for (int s=0; s < NUM_SEG; s++) begin
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byte_count = 0;
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for (int b = SEG_DATA_WIDTH/8-1; b >= 0; b--) begin
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if (pay.size() > 0) begin
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assert (lbus_out[s].data[b*8 +: 8] == pay.pop_front()) else $error("Data Mismatch");
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byte_count++;
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end
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end
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assert (lbus_out[s].ena == (byte_count > 0) ) else $error("Ena Mismatch");
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if (lbus_out[s].ena) begin
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if (first_clk && s==0) begin
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assert (lbus_out[s].sop == 1) else $error("Sop not set");
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end else begin
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assert (lbus_out[s].sop == 0) else $error("Sop Set");
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end
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assert (lbus_out[s].mty == (SEG_BYTES-byte_count) % SEG_BYTES) else $error("Mty Mismatch");
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assert (lbus_out[s].eop != (pay.size() > 0) ) else $error("Eop Mismatch");
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assert (lbus_out[s].err == 0) else $error("Err Mismatch"); // not checking error yet
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end else begin
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assert (lbus_out[s].sop == 0) else $error("Sop Set while disabled");
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assert (lbus_out[s].mty == 0) else $error("Mty set while disabled");
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assert (lbus_out[s].eop == 0) else $error("Eop set while disabled");
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assert (lbus_out[s].err == 0) else $error("Err set while disabled");
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end
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end // segment loop
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first_clk=0;
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end // first segment is enabled
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end else begin //not lbus_rdy
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for (int s=0; s < NUM_SEG; s++) begin
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assert (lbus_out[s].ena == 0) else $error("Idle Ena set");
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assert (lbus_out[s].err == 0) else $error("Idle Err set");
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assert (lbus_out[s].sop == 0) else $error("Idle Sop set");
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assert (lbus_out[s].eop == 0) else $error("Idle Eop set");
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assert (lbus_out[s].mty == 0) else $error("Idle Mty non zero");
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end
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end
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end // while pay.size > 0
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end // foreach packet
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endtask : check_lbus;
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task automatic test_transfers(int num_samples[$]);
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automatic AxisPacket_t send[$];
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automatic AxisPacket_t expected[$];
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automatic int sample_sum = 0;
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test.start_test({TEST_NAME,"Test Transfer"}, 200us);
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foreach (num_samples[i]) begin
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automatic raw_pkt_t pay;
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expected[i] = new;
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send[i] = new;
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get_ramp_raw_pkt(.num_samps(num_samples[i]),.ramp_start((sample_sum)%256),
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.ramp_inc(1),.pkt(pay),.SWIDTH(8));
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sample_sum += num_samples[i];
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send[i].push_bytes(pay);
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// rebuild the expected packet for comparison without the preamble
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expected[i].push_bytes(pay);
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end
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fork
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begin // tx_thread
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foreach (send[i]) begin
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axi.put(send[i]);
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end
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end
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begin //rx_thread
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check_lbus(expected);
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end
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join
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test.end_test();
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endtask : test_transfers
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//----------------------------------------------------
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// Main test loop
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//----------------------------------------------------
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initial begin : tb_main
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automatic int num_samples[$];
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automatic int random_value;
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clk_gen.reset();
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// stalling is not allowed by whoever is reading the MAC
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// i.e. ready is ignored
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axi.set_master_stall_prob(0);
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axi.run();
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test_reset();
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$display("Fixed Sequences");
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num_samples = {64,65,66,67,68,69,70,71};
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test_transfers(num_samples);
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num_samples = {64,128,256,512,256,64,64,64};
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test_transfers(num_samples);
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num_samples = {65,64,64,64,64,64,64,64};
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test_transfers(num_samples);
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num_samples = {65,64,80,80,80,80,80,80};
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test_transfers(num_samples);
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num_samples = {64,64,96,80,96,80,96,80};
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test_transfers(num_samples);
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$display("Tons of 64");
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num_samples.delete();
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repeat(1000) begin
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num_samples.push_back(64);
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end
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test_transfers(num_samples);
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$display("Tons of 65");
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num_samples.delete();
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repeat(1000) begin
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num_samples.push_back(65);
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end
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test_transfers(num_samples);
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$display("Tons of Random");
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num_samples.delete();
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repeat(1000) begin
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random_value = $urandom_range(64,512);
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num_samples.push_back(random_value);
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end
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test_transfers(num_samples);
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// End the TB, but don't $finish, since we don't want to kill other
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// instances of this testbench that may be running.
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test.end_tb(0);
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// Kill the clocks to end this instance of the testbench
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clk_gen.kill();
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end // initial begin
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endmodule
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@@ -0,0 +1,22 @@
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//
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// Copyright 2021 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
|
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//
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// Module: lbus_all_tb
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//
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// Description:
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//
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// Testbench for LBU<->AXI
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//
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module lbus_all_tb #(
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/* no PARAM */
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)(
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/* no IO */
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);
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lbus_axi_tb #(.TEST_NAME("L2A")) L2A ();
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axi_lbus_tb #(.TEST_NAME("A2L")) A2L ();
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endmodule
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@@ -0,0 +1,343 @@
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//
|
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// Copyright 2021 Ettus Research, a National Instruments Brand
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
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//
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// Module: lbus_axi_tb
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//
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// Description:
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//
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// Testbench for eth_interface
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//
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module lbus_axi_tb #(
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parameter TEST_NAME = ""
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)(
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/* no IO */
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);
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// Include macros and time declarations for use with PkgTestExec
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`define TEST_EXEC_OBJ test
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`include "test_exec.svh"
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import PkgAxiStreamBfm::*;
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import PkgEthernet::*;
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import PkgTestExec::*;
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import PkgEth100gLbus::*;
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localparam DATA_WIDTH = 512;
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localparam USER_WIDTH = $clog2(DATA_WIDTH/8)+1;
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localparam NUM_SEG = 4;
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localparam SEG_DATA_WIDTH = DATA_WIDTH/NUM_SEG;
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localparam SEG_BYTES = SEG_DATA_WIDTH/8;
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//----------------------------------------------------
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// clocks
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//----------------------------------------------------
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logic clk;
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logic rst;
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sim_clock_gen #(.PERIOD(5), .AUTOSTART(1))
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clk_gen (.clk(clk), .rst(rst));
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//----------------------------------------------------
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//interfaces
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//----------------------------------------------------
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AxiStreamIf #(.DATA_WIDTH(DATA_WIDTH),.USER_WIDTH(USER_WIDTH))
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axis (clk, rst);
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AxiStreamIf #(.DATA_WIDTH(DATA_WIDTH),.USER_WIDTH(USER_WIDTH))
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axig (clk, rst);
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//----------------------------------------------------
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// DUT
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//----------------------------------------------------
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lbus_t lbus_in [NUM_SEG-1:0];
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eth_100g_lbus2axi #(.FIFO_DEPTH(5),.NUM_SEG(NUM_SEG)) DUT (
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.axis(axis),
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.lbus_in(lbus_in)
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);
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//----------------------------------------------------
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// Xilinx golden model
|
||||
// When Xilinx is generated with an AXI interface xilinx prints
|
||||
// a lbus2axis converter that has trouble meeting timing
|
||||
// this is preserved to allow comparison to that
|
||||
// TODO: remove when timing is passing and refactor is done
|
||||
//----------------------------------------------------
|
||||
/*
|
||||
eth_100g_bd_cmac_usplus_0_0_lbus2axis_segmented_top GOLD (
|
||||
.core_clk(clk),
|
||||
.core_rst(rst),
|
||||
|
||||
// AXIS IF
|
||||
.axis_tvalid(axig.tvalid),
|
||||
.axis_tdata(axig.tdata),
|
||||
.axis_tlast(axig.tlast),
|
||||
.axis_tkeep(axig.tkeep),
|
||||
.axis_tuser(),
|
||||
// Segment 0
|
||||
.lbus_ena0(lbus_in[0].ena),
|
||||
.lbus_data0(lbus_in[0].data),
|
||||
.lbus_sop0(lbus_in[0].sop),
|
||||
.lbus_eop0(lbus_in[0].eop),
|
||||
.lbus_mty0(lbus_in[0].mty),
|
||||
.lbus_err0(lbus_in[0].err),
|
||||
// Segment 1
|
||||
.lbus_ena1(lbus_in[1].ena),
|
||||
.lbus_data1(lbus_in[1].data),
|
||||
.lbus_sop1(lbus_in[1].sop),
|
||||
.lbus_eop1(lbus_in[1].eop),
|
||||
.lbus_mty1(lbus_in[1].mty),
|
||||
.lbus_err1(lbus_in[1].err),
|
||||
// Segment 2
|
||||
.lbus_ena2(lbus_in[2].ena),
|
||||
.lbus_data2(lbus_in[2].data),
|
||||
.lbus_sop2(lbus_in[2].sop),
|
||||
.lbus_eop2(lbus_in[2].eop),
|
||||
.lbus_mty2(lbus_in[2].mty),
|
||||
.lbus_err2(lbus_in[2].err),
|
||||
// Segment 3
|
||||
.lbus_ena3(lbus_in[3].ena),
|
||||
.lbus_data3(lbus_in[3].data),
|
||||
.lbus_sop3(lbus_in[3].sop),
|
||||
.lbus_eop3(lbus_in[3].eop),
|
||||
.lbus_mty3(lbus_in[3].mty),
|
||||
.lbus_err3(lbus_in[3].err)
|
||||
);
|
||||
*/
|
||||
//----------------------------------------------------
|
||||
//BFMS
|
||||
//----------------------------------------------------
|
||||
|
||||
TestExec test = new();
|
||||
AxiStreamBfm #(.DATA_WIDTH(DATA_WIDTH),.USER_WIDTH(USER_WIDTH)) axi =
|
||||
new(.slave(axis),.master(null));
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Tests
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
// use Test timeout to check reset goes away
|
||||
task test_reset();
|
||||
test.start_test({TEST_NAME,"Wait for Reset"}, 10us);
|
||||
wait(!rst);
|
||||
repeat (10) @(posedge clk);
|
||||
test.end_test();
|
||||
endtask : test_reset
|
||||
|
||||
typedef AxiStreamPacket #(DATA_WIDTH,USER_WIDTH) AxisPacket_t;
|
||||
typedef XportStreamPacket #(DATA_WIDTH) XportPacket_t;
|
||||
|
||||
task automatic clear_lbus_in();
|
||||
for (int i=0 ; i < NUM_SEG ; ++i) begin
|
||||
lbus_in[i].data = 'b0;
|
||||
lbus_in[i].mty = 'b0;
|
||||
lbus_in[i].sop = 1'b0;
|
||||
lbus_in[i].eop = 1'b0;
|
||||
lbus_in[i].err = 1'b0;
|
||||
lbus_in[i].ena = 1'b0;
|
||||
end
|
||||
endtask : clear_lbus_in;
|
||||
|
||||
task automatic send_lbus(AxisPacket_t packets[$]);
|
||||
|
||||
int seg = 0;
|
||||
int b = 0;
|
||||
int idle_insert = 0;
|
||||
|
||||
// loop over packets
|
||||
foreach(packets[i]) begin
|
||||
automatic raw_pkt_t pay;
|
||||
pay = packets[i].dump_bytes;
|
||||
// set for the first segment
|
||||
lbus_in[seg].sop = 1;
|
||||
// empty this packets payload
|
||||
while (pay.size() > 0) begin
|
||||
lbus_in[seg].ena = 1;
|
||||
lbus_in[seg].data |= pay.pop_front()<<(SEG_DATA_WIDTH-b*8-8);
|
||||
if (pay.size() == 0) begin
|
||||
lbus_in[seg].eop = 1;
|
||||
lbus_in[seg].mty = SEG_DATA_WIDTH-1-b;
|
||||
end
|
||||
if (seg == NUM_SEG-1 && b == SEG_DATA_WIDTH/8-1) begin
|
||||
@(posedge clk);
|
||||
clear_lbus_in();
|
||||
idle_insert++;
|
||||
// insert period idle period
|
||||
if (idle_insert > 2) begin
|
||||
@(posedge clk);
|
||||
idle_insert =0;
|
||||
end
|
||||
end
|
||||
b = (b+1) % (SEG_DATA_WIDTH/8);
|
||||
if (b==0) begin
|
||||
seg = (seg+1) % NUM_SEG;
|
||||
end
|
||||
end // pay.size > 0
|
||||
if (b != 0) begin
|
||||
seg = (seg+1) % NUM_SEG;
|
||||
if (seg == 0) begin
|
||||
@(posedge clk);
|
||||
clear_lbus_in();
|
||||
idle_insert++;
|
||||
// insert period idle period
|
||||
if (idle_insert > 2) begin
|
||||
@(posedge clk);
|
||||
idle_insert =0;
|
||||
end
|
||||
end
|
||||
b = 0;
|
||||
end
|
||||
|
||||
// 25% of the time we start a new packet
|
||||
if ($urandom_range(99) < 25) begin
|
||||
b = 0;
|
||||
seg = 0;
|
||||
// 25% of the time add an idle cycle
|
||||
if ($urandom_range(99) < 25) begin
|
||||
@(posedge clk);
|
||||
clear_lbus_in();
|
||||
idle_insert++;
|
||||
// insert period idle period
|
||||
if (idle_insert > 2) begin
|
||||
idle_insert =0;
|
||||
@(posedge clk);
|
||||
end
|
||||
@(posedge clk);
|
||||
end else begin
|
||||
@(posedge clk);
|
||||
clear_lbus_in();
|
||||
idle_insert++;
|
||||
// insert period idle period
|
||||
if (idle_insert > 2) begin
|
||||
idle_insert =0;
|
||||
@(posedge clk);
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
end // foreach packet
|
||||
|
||||
@(posedge clk);
|
||||
clear_lbus_in();
|
||||
|
||||
endtask : send_lbus;
|
||||
|
||||
task automatic compare_packet(AxisPacket_t actual, expected);
|
||||
|
||||
automatic XportPacket_t actual_copy = new();
|
||||
automatic XportPacket_t expected_copy = new();
|
||||
actual_copy.import_axis(actual);
|
||||
expected_copy.import_axis(expected);
|
||||
|
||||
expected_copy.tkeep_to_tuser();
|
||||
actual_copy.clear_unused_bytes();
|
||||
|
||||
if (!expected_copy.equal(actual_copy)) begin
|
||||
$display("Expected");
|
||||
expected_copy.print();
|
||||
$display("Actual");
|
||||
actual_copy.print();
|
||||
if (!expected_copy.equal(actual_copy))
|
||||
$error("ERROR :: packet mismatch");
|
||||
|
||||
end
|
||||
|
||||
endtask : compare_packet;
|
||||
|
||||
task automatic test_transfers(int num_samples[$]);
|
||||
automatic AxisPacket_t send[$];
|
||||
automatic AxisPacket_t expected[$];
|
||||
automatic int sample_sum = 0;
|
||||
|
||||
test.start_test({TEST_NAME,"Test Transfer"}, 200us);
|
||||
|
||||
foreach (num_samples[i]) begin
|
||||
automatic raw_pkt_t pay;
|
||||
|
||||
expected[i] = new;
|
||||
send[i] = new;
|
||||
|
||||
get_ramp_raw_pkt(.num_samps(num_samples[i]),.ramp_start((sample_sum)%256),
|
||||
.ramp_inc(1),.pkt(pay),.SWIDTH(8));
|
||||
sample_sum += num_samples[i];
|
||||
send[i].push_bytes(pay);
|
||||
|
||||
// rebuild the expected packet for comparison without the preamble
|
||||
expected[i].push_bytes(pay);
|
||||
end
|
||||
|
||||
fork
|
||||
begin // tx_thread
|
||||
send_lbus(send);
|
||||
end
|
||||
begin //rx_thread
|
||||
foreach(expected[i]) begin
|
||||
automatic AxisPacket_t actual;
|
||||
axi.get(actual);
|
||||
compare_packet(actual,expected[i]);
|
||||
end
|
||||
end
|
||||
join
|
||||
|
||||
test.end_test();
|
||||
endtask : test_transfers
|
||||
|
||||
//----------------------------------------------------
|
||||
// Main test loop
|
||||
//----------------------------------------------------
|
||||
initial begin : tb_main
|
||||
automatic int num_samples[$];
|
||||
automatic int random_value;
|
||||
clk_gen.reset();
|
||||
|
||||
// stalling is not allowed by whoever is reading the MAC
|
||||
// i.e. ready is ignored
|
||||
axi.slave_tready_init = 1'b1;
|
||||
axi.set_master_stall_prob(0);
|
||||
axi.set_slave_stall_prob(0);
|
||||
axi.run();
|
||||
clear_lbus_in();
|
||||
test_reset();
|
||||
|
||||
$display("Fixed Sequences");
|
||||
num_samples = {64,65,66,67,68,69,70,71};
|
||||
test_transfers(num_samples);
|
||||
num_samples = {64,128,256,512,256,64,64,64};
|
||||
test_transfers(num_samples);
|
||||
num_samples = {65,64,64,64,64,64,64,64};
|
||||
test_transfers(num_samples);
|
||||
num_samples = {65,64,80,80,80,80,80,80};
|
||||
test_transfers(num_samples);
|
||||
num_samples = {64,64,96,80,96,80,96,80};
|
||||
test_transfers(num_samples);
|
||||
$display("Tons of 64");
|
||||
num_samples.delete();
|
||||
repeat(1000) begin
|
||||
num_samples.push_back(64);
|
||||
end
|
||||
test_transfers(num_samples);
|
||||
$display("Tons of 65");
|
||||
num_samples.delete();
|
||||
repeat(1000) begin
|
||||
num_samples.push_back(65);
|
||||
end
|
||||
test_transfers(num_samples);
|
||||
$display("Tons of Random");
|
||||
num_samples.delete();
|
||||
repeat(1000) begin
|
||||
random_value = $urandom_range(64,512);
|
||||
num_samples.push_back(random_value);
|
||||
end
|
||||
test_transfers(num_samples);
|
||||
|
||||
|
||||
// End the TB, but don't $finish, since we don't want to kill other
|
||||
// instances of this testbench that may be running.
|
||||
test.end_tb(0);
|
||||
|
||||
// Kill the clocks to end this instance of the testbench
|
||||
clk_gen.kill();
|
||||
end // initial begin
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user