fpga: x400: Add support for X410 motherboard FPGA
Co-authored-by: Andrew Moch <Andrew.Moch@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Michael Auchter <michael.auchter@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Hector Rubio <hrubio@ni.com> Original-commit: 6d3765605262016a80f71e36357f749ea35cbe5a
This commit is contained in:
Wade Fife
committed by
Aaron Rossetto
Aaron Rossetto
co-authored by
Andrew Moch
Daniel Jepson
Javier Valenzuela
Joerg Hofrichter
Kumaran Subramoniam
Max Köhler
Michael Auchter
Paul Butler
Hector Rubio
Andrew Moch
Daniel Jepson
Javier Valenzuela
Joerg Hofrichter
Kumaran Subramoniam
Max Köhler
Michael Auchter
Paul Butler
Hector Rubio
parent
bfef20ea45
commit
61782b02d7
@@ -0,0 +1,41 @@
|
||||
#
|
||||
# Copyright 2021 Ettus Research, a National Instruments Brand
|
||||
#
|
||||
# SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
#
|
||||
|
||||
include $(TOOLS_DIR)/make/viv_ip_builder.mak
|
||||
|
||||
IP_AXI_INTERCONNECT_ETH_HDL_SRCS = $(addprefix $(IP_DIR)/axi_interconnect_eth_bd/, \
|
||||
axi_interconnect_eth.sv \
|
||||
)
|
||||
|
||||
IP_AXI_INTERCONNECT_ETH_HDL_SIM_SRCS = $(wildcard $(addprefix $(IP_BUILD_DIR)/axi_interconnect_eth_bd/axi_interconnect_eth_bd/, \
|
||||
sim/axi_interconnect_eth_bd.v\
|
||||
ip/axi_interconnect_eth_bd_xbar_0/sim/axi_interconnect_eth_bd_xbar_0.v\
|
||||
ipshared/*/simulation/fifo_generator_vlog_beh.v\
|
||||
ipshared/*/hdl/*.v\
|
||||
))
|
||||
|
||||
IP_AXI_INTERCONNECT_ETH_ORIG_SRCS = $(addprefix $(IP_DIR)/axi_interconnect_eth_bd/, \
|
||||
axi_interconnect_eth_bd.tcl \
|
||||
)
|
||||
|
||||
IP_AXI_INTERCONNECT_ETH_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_interconnect_eth_bd/, \
|
||||
axi_interconnect_eth_bd.tcl \
|
||||
)
|
||||
|
||||
IP_AXI_INTERCONNECT_ETH_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_interconnect_eth_bd/, \
|
||||
axi_interconnect_eth_bd/axi_interconnect_eth_bd.bd \
|
||||
)
|
||||
|
||||
BD_AXI_INTERCONNECT_ETH_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_interconnect_eth_bd/, \
|
||||
axi_interconnect_eth_bd.bd.out \
|
||||
axi_interconnect_eth_bd/synth/axi_interconnect_eth_bd.v \
|
||||
axi_interconnect_eth_bd/axi_interconnect_eth_bd_ooc.xdc \
|
||||
)
|
||||
|
||||
|
||||
|
||||
$(IP_AXI_INTERCONNECT_ETH_BD_SRCS) $(BD_AXI_INTERCONNECT_ETH_BD_OUTS) $(IP_AXI_INTERCONNECT_ETH_BDTCL_SRCS): $(IP_AXI_INTERCONNECT_ETH_ORIG_SRCS)
|
||||
$(call BUILD_VIVADO_BDTCL,axi_interconnect_eth_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi)
|
||||
@@ -0,0 +1,98 @@
|
||||
//
|
||||
// Copyright 2021 Ettus Research, A National Instruments Brand
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: axi_interconnect_eth
|
||||
//
|
||||
// Description:
|
||||
//
|
||||
// Wrapper for the Xilinx AXI Lite interconnect block
|
||||
//
|
||||
|
||||
module axi_interconnect_eth (
|
||||
// All interfaces on s_axi_eth.clk domain
|
||||
AxiLiteIf.master m_axi_dma[3:0], // maps to CPU_DMA +0x00000-0x07FFF
|
||||
AxiLiteIf.master m_axi_misc[3:0], // maps to nixge +0x08000-0x09FFF
|
||||
// UIO +0x0A000-0x0BFFF
|
||||
AxiLiteIf.master m_axi_mac[3:0], // maps to 100G Mac +0x0C000-0x0DFFF
|
||||
|
||||
AxiLiteIf.slave s_axi_eth // incoming axi_net bus
|
||||
);
|
||||
|
||||
|
||||
// AxiLiteIf_v has no procedural assignments so it can be
|
||||
// driven by a port.
|
||||
`include "../../../../lib/axi4lite_sv/axi_lite.vh"
|
||||
AxiLiteIf_v #(32,40)
|
||||
m_axi_dma_v[3:0](.clk(s_axi_eth.clk),.rst(s_axi_eth.rst));
|
||||
AxiLiteIf_v #(32,40)
|
||||
m_axi_misc_v[3:0](.clk(s_axi_eth.clk),.rst(s_axi_eth.rst));
|
||||
AxiLiteIf_v #(32,40)
|
||||
m_axi_mac_v[3:0](.clk(s_axi_eth.clk),.rst(s_axi_eth.rst));
|
||||
AxiLiteIf_v #(32,40)
|
||||
s_axi_eth_v(.clk(s_axi_eth.clk),.rst(s_axi_eth.rst));
|
||||
|
||||
// O = I;(O ,I )
|
||||
always_comb begin `AXI4LITE_ASSIGN(m_axi_dma[0],m_axi_dma_v[0]) end
|
||||
always_comb begin `AXI4LITE_ASSIGN(m_axi_dma[1],m_axi_dma_v[1]) end
|
||||
always_comb begin `AXI4LITE_ASSIGN(m_axi_dma[2],m_axi_dma_v[2]) end
|
||||
always_comb begin `AXI4LITE_ASSIGN(m_axi_dma[3],m_axi_dma_v[3]) end
|
||||
always_comb begin `AXI4LITE_ASSIGN(m_axi_misc[0],m_axi_misc_v[0]) end
|
||||
always_comb begin `AXI4LITE_ASSIGN(m_axi_misc[1],m_axi_misc_v[1]) end
|
||||
always_comb begin `AXI4LITE_ASSIGN(m_axi_misc[2],m_axi_misc_v[2]) end
|
||||
always_comb begin `AXI4LITE_ASSIGN(m_axi_misc[3],m_axi_misc_v[3]) end
|
||||
always_comb begin `AXI4LITE_ASSIGN(m_axi_mac[0],m_axi_mac_v[0]) end
|
||||
always_comb begin `AXI4LITE_ASSIGN(m_axi_mac[1],m_axi_mac_v[1]) end
|
||||
always_comb begin `AXI4LITE_ASSIGN(m_axi_mac[2],m_axi_mac_v[2]) end
|
||||
always_comb begin `AXI4LITE_ASSIGN(m_axi_mac[3],m_axi_mac_v[3]) end
|
||||
always_comb begin `AXI4LITE_ASSIGN(s_axi_eth_v,s_axi_eth) end
|
||||
|
||||
axi_interconnect_eth_bd axi_interconnect_eth_bd_i
|
||||
(
|
||||
`AXI4LITE_PORT_ASSIGN_NR(m_axi_dma0,m_axi_dma_v[0])
|
||||
.m_axi_dma0_arprot(),
|
||||
.m_axi_dma0_awprot(),
|
||||
`AXI4LITE_PORT_ASSIGN_NR(m_axi_dma1,m_axi_dma_v[1])
|
||||
.m_axi_dma1_arprot(),
|
||||
.m_axi_dma1_awprot(),
|
||||
`AXI4LITE_PORT_ASSIGN_NR(m_axi_dma2,m_axi_dma_v[2])
|
||||
.m_axi_dma2_arprot(),
|
||||
.m_axi_dma2_awprot(),
|
||||
`AXI4LITE_PORT_ASSIGN_NR(m_axi_dma3,m_axi_dma_v[3])
|
||||
.m_axi_dma3_arprot(),
|
||||
.m_axi_dma3_awprot(),
|
||||
|
||||
`AXI4LITE_PORT_ASSIGN_NR(m_axi_mac0,m_axi_mac_v[0])
|
||||
.m_axi_mac0_arprot(),
|
||||
.m_axi_mac0_awprot(),
|
||||
`AXI4LITE_PORT_ASSIGN_NR(m_axi_mac1,m_axi_mac_v[1])
|
||||
.m_axi_mac1_arprot(),
|
||||
.m_axi_mac1_awprot(),
|
||||
`AXI4LITE_PORT_ASSIGN_NR(m_axi_mac2,m_axi_mac_v[2])
|
||||
.m_axi_mac2_arprot(),
|
||||
.m_axi_mac2_awprot(),
|
||||
`AXI4LITE_PORT_ASSIGN_NR(m_axi_mac3,m_axi_mac_v[3])
|
||||
.m_axi_mac3_arprot(),
|
||||
.m_axi_mac3_awprot(),
|
||||
|
||||
`AXI4LITE_PORT_ASSIGN_NR(m_axi_misc0,m_axi_misc_v[0])
|
||||
.m_axi_misc0_arprot(),
|
||||
.m_axi_misc0_awprot(),
|
||||
`AXI4LITE_PORT_ASSIGN_NR(m_axi_misc1,m_axi_misc_v[1])
|
||||
.m_axi_misc1_arprot(),
|
||||
.m_axi_misc1_awprot(),
|
||||
`AXI4LITE_PORT_ASSIGN_NR(m_axi_misc2,m_axi_misc_v[2])
|
||||
.m_axi_misc2_arprot(),
|
||||
.m_axi_misc2_awprot(),
|
||||
`AXI4LITE_PORT_ASSIGN_NR(m_axi_misc3,m_axi_misc_v[3])
|
||||
.m_axi_misc3_arprot(),
|
||||
.m_axi_misc3_awprot(),
|
||||
|
||||
`AXI4LITE_PORT_ASSIGN_NR(s_axi_eth,s_axi_eth_v)
|
||||
.s_axi_eth_arprot(3'b0),
|
||||
.s_axi_eth_awprot(3'b0),
|
||||
.clk40(s_axi_eth.clk),
|
||||
.clk40_rstn(!s_axi_eth.rst));
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,462 @@
|
||||
|
||||
################################################################
|
||||
# This is a generated script based on design: axi_interconnect_eth_bd
|
||||
#
|
||||
# Though there are limitations about the generated script,
|
||||
# the main purpose of this utility is to make learning
|
||||
# IP Integrator Tcl commands easier.
|
||||
################################################################
|
||||
|
||||
namespace eval _tcl {
|
||||
proc get_script_folder {} {
|
||||
set script_path [file normalize [info script]]
|
||||
set script_folder [file dirname $script_path]
|
||||
return $script_folder
|
||||
}
|
||||
}
|
||||
variable script_folder
|
||||
set script_folder [_tcl::get_script_folder]
|
||||
|
||||
################################################################
|
||||
# Check if script is running in correct Vivado version.
|
||||
################################################################
|
||||
set scripts_vivado_version 2019.1
|
||||
set current_vivado_version [version -short]
|
||||
|
||||
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
|
||||
puts ""
|
||||
catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
|
||||
|
||||
return 1
|
||||
}
|
||||
|
||||
################################################################
|
||||
# START
|
||||
################################################################
|
||||
|
||||
# To test this script, run the following commands from Vivado Tcl console:
|
||||
# source axi_interconnect_eth_bd_script.tcl
|
||||
|
||||
# If there is no project opened, this script will create a
|
||||
# project, but make sure you do not have an existing project
|
||||
# <./myproj/project_1.xpr> in the current working folder.
|
||||
|
||||
set list_projs [get_projects -quiet]
|
||||
if { $list_projs eq "" } {
|
||||
create_project project_1 myproj -part xczu28dr-ffvg1517-1-e
|
||||
}
|
||||
|
||||
|
||||
# CHANGE DESIGN NAME HERE
|
||||
variable design_name
|
||||
set design_name axi_interconnect_eth_bd
|
||||
|
||||
# If you do not already have an existing IP Integrator design open,
|
||||
# you can create a design using the following command:
|
||||
# create_bd_design $design_name
|
||||
|
||||
# Creating design if needed
|
||||
set errMsg ""
|
||||
set nRet 0
|
||||
|
||||
set cur_design [current_bd_design -quiet]
|
||||
set list_cells [get_bd_cells -quiet]
|
||||
|
||||
if { ${design_name} eq "" } {
|
||||
# USE CASES:
|
||||
# 1) Design_name not set
|
||||
|
||||
set errMsg "Please set the variable <design_name> to a non-empty value."
|
||||
set nRet 1
|
||||
|
||||
} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
|
||||
# USE CASES:
|
||||
# 2): Current design opened AND is empty AND names same.
|
||||
# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
|
||||
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
|
||||
|
||||
if { $cur_design ne $design_name } {
|
||||
common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
|
||||
set design_name [get_property NAME $cur_design]
|
||||
}
|
||||
common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
|
||||
|
||||
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
|
||||
# USE CASES:
|
||||
# 5) Current design opened AND has components AND same names.
|
||||
|
||||
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
|
||||
set nRet 1
|
||||
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
|
||||
# USE CASES:
|
||||
# 6) Current opened design, has components, but diff names, design_name exists in project.
|
||||
# 7) No opened design, design_name exists in project.
|
||||
|
||||
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
|
||||
set nRet 2
|
||||
|
||||
} else {
|
||||
# USE CASES:
|
||||
# 8) No opened design, design_name not in project.
|
||||
# 9) Current opened design, has components, but diff names, design_name not in project.
|
||||
|
||||
common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
|
||||
|
||||
create_bd_design $design_name
|
||||
|
||||
common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
|
||||
current_bd_design $design_name
|
||||
|
||||
}
|
||||
|
||||
common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
|
||||
|
||||
if { $nRet != 0 } {
|
||||
catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
|
||||
return $nRet
|
||||
}
|
||||
|
||||
set bCheckIPsPassed 1
|
||||
##################################################################
|
||||
# CHECK IPs
|
||||
##################################################################
|
||||
set bCheckIPs 1
|
||||
if { $bCheckIPs == 1 } {
|
||||
set list_check_ips "\
|
||||
"
|
||||
|
||||
set list_ips_missing ""
|
||||
common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
|
||||
|
||||
foreach ip_vlnv $list_check_ips {
|
||||
set ip_obj [get_ipdefs -all $ip_vlnv]
|
||||
if { $ip_obj eq "" } {
|
||||
lappend list_ips_missing $ip_vlnv
|
||||
}
|
||||
}
|
||||
|
||||
if { $list_ips_missing ne "" } {
|
||||
catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
|
||||
set bCheckIPsPassed 0
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
if { $bCheckIPsPassed != 1 } {
|
||||
common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
|
||||
return 3
|
||||
}
|
||||
|
||||
##################################################################
|
||||
# DESIGN PROCs
|
||||
##################################################################
|
||||
|
||||
|
||||
|
||||
# Procedure to create entire design; Provide argument to make
|
||||
# procedure reusable. If parentCell is "", will use root.
|
||||
proc create_root_design { parentCell } {
|
||||
|
||||
variable script_folder
|
||||
variable design_name
|
||||
|
||||
if { $parentCell eq "" } {
|
||||
set parentCell [get_bd_cells /]
|
||||
}
|
||||
|
||||
# Get object for parentCell
|
||||
set parentObj [get_bd_cells $parentCell]
|
||||
if { $parentObj == "" } {
|
||||
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Make sure parentObj is hier blk
|
||||
set parentType [get_property TYPE $parentObj]
|
||||
if { $parentType ne "hier" } {
|
||||
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
return
|
||||
}
|
||||
|
||||
# Save current instance; Restore later
|
||||
set oldCurInst [current_bd_instance .]
|
||||
|
||||
# Set parent object as current
|
||||
current_bd_instance $parentObj
|
||||
|
||||
|
||||
# Create interface ports
|
||||
set m_axi_dma0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_dma0 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ADDR_WIDTH {40} \
|
||||
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
|
||||
CONFIG.DATA_WIDTH {32} \
|
||||
CONFIG.FREQ_HZ {40000000} \
|
||||
CONFIG.HAS_BURST {0} \
|
||||
CONFIG.HAS_CACHE {0} \
|
||||
CONFIG.HAS_LOCK {0} \
|
||||
CONFIG.HAS_QOS {0} \
|
||||
CONFIG.HAS_REGION {0} \
|
||||
CONFIG.PROTOCOL {AXI4LITE} \
|
||||
] $m_axi_dma0
|
||||
|
||||
set m_axi_dma1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_dma1 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ADDR_WIDTH {40} \
|
||||
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
|
||||
CONFIG.DATA_WIDTH {32} \
|
||||
CONFIG.FREQ_HZ {40000000} \
|
||||
CONFIG.HAS_BURST {0} \
|
||||
CONFIG.HAS_CACHE {0} \
|
||||
CONFIG.HAS_LOCK {0} \
|
||||
CONFIG.HAS_QOS {0} \
|
||||
CONFIG.HAS_REGION {0} \
|
||||
CONFIG.PROTOCOL {AXI4LITE} \
|
||||
] $m_axi_dma1
|
||||
|
||||
set m_axi_dma2 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_dma2 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ADDR_WIDTH {40} \
|
||||
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
|
||||
CONFIG.DATA_WIDTH {32} \
|
||||
CONFIG.FREQ_HZ {40000000} \
|
||||
CONFIG.HAS_BURST {0} \
|
||||
CONFIG.HAS_CACHE {0} \
|
||||
CONFIG.HAS_LOCK {0} \
|
||||
CONFIG.HAS_QOS {0} \
|
||||
CONFIG.HAS_REGION {0} \
|
||||
CONFIG.PROTOCOL {AXI4LITE} \
|
||||
] $m_axi_dma2
|
||||
|
||||
set m_axi_dma3 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_dma3 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ADDR_WIDTH {40} \
|
||||
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
|
||||
CONFIG.DATA_WIDTH {32} \
|
||||
CONFIG.FREQ_HZ {40000000} \
|
||||
CONFIG.HAS_BURST {0} \
|
||||
CONFIG.HAS_CACHE {0} \
|
||||
CONFIG.HAS_LOCK {0} \
|
||||
CONFIG.HAS_QOS {0} \
|
||||
CONFIG.HAS_REGION {0} \
|
||||
CONFIG.PROTOCOL {AXI4LITE} \
|
||||
] $m_axi_dma3
|
||||
|
||||
set m_axi_mac0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_mac0 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ADDR_WIDTH {40} \
|
||||
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
|
||||
CONFIG.DATA_WIDTH {32} \
|
||||
CONFIG.FREQ_HZ {40000000} \
|
||||
CONFIG.HAS_BURST {0} \
|
||||
CONFIG.HAS_CACHE {0} \
|
||||
CONFIG.HAS_LOCK {0} \
|
||||
CONFIG.HAS_PROT {0} \
|
||||
CONFIG.HAS_QOS {0} \
|
||||
CONFIG.HAS_REGION {0} \
|
||||
CONFIG.NUM_READ_OUTSTANDING {2} \
|
||||
CONFIG.NUM_WRITE_OUTSTANDING {2} \
|
||||
CONFIG.PROTOCOL {AXI4LITE} \
|
||||
] $m_axi_mac0
|
||||
|
||||
set m_axi_mac1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_mac1 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ADDR_WIDTH {40} \
|
||||
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
|
||||
CONFIG.DATA_WIDTH {32} \
|
||||
CONFIG.FREQ_HZ {40000000} \
|
||||
CONFIG.HAS_BURST {0} \
|
||||
CONFIG.HAS_CACHE {0} \
|
||||
CONFIG.HAS_LOCK {0} \
|
||||
CONFIG.HAS_QOS {0} \
|
||||
CONFIG.HAS_REGION {0} \
|
||||
CONFIG.PROTOCOL {AXI4LITE} \
|
||||
] $m_axi_mac1
|
||||
|
||||
set m_axi_mac2 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_mac2 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ADDR_WIDTH {40} \
|
||||
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
|
||||
CONFIG.DATA_WIDTH {32} \
|
||||
CONFIG.FREQ_HZ {40000000} \
|
||||
CONFIG.HAS_BURST {0} \
|
||||
CONFIG.HAS_CACHE {0} \
|
||||
CONFIG.HAS_LOCK {0} \
|
||||
CONFIG.HAS_QOS {0} \
|
||||
CONFIG.HAS_REGION {0} \
|
||||
CONFIG.PROTOCOL {AXI4LITE} \
|
||||
] $m_axi_mac2
|
||||
|
||||
set m_axi_mac3 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_mac3 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ADDR_WIDTH {40} \
|
||||
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
|
||||
CONFIG.DATA_WIDTH {32} \
|
||||
CONFIG.FREQ_HZ {40000000} \
|
||||
CONFIG.HAS_BURST {0} \
|
||||
CONFIG.HAS_CACHE {0} \
|
||||
CONFIG.HAS_LOCK {0} \
|
||||
CONFIG.HAS_QOS {0} \
|
||||
CONFIG.HAS_REGION {0} \
|
||||
CONFIG.PROTOCOL {AXI4LITE} \
|
||||
] $m_axi_mac3
|
||||
|
||||
set m_axi_misc0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_misc0 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ADDR_WIDTH {40} \
|
||||
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
|
||||
CONFIG.DATA_WIDTH {32} \
|
||||
CONFIG.FREQ_HZ {40000000} \
|
||||
CONFIG.HAS_BURST {0} \
|
||||
CONFIG.HAS_CACHE {0} \
|
||||
CONFIG.HAS_LOCK {0} \
|
||||
CONFIG.HAS_PROT {0} \
|
||||
CONFIG.HAS_QOS {0} \
|
||||
CONFIG.HAS_REGION {0} \
|
||||
CONFIG.NUM_READ_OUTSTANDING {2} \
|
||||
CONFIG.NUM_WRITE_OUTSTANDING {2} \
|
||||
CONFIG.PROTOCOL {AXI4LITE} \
|
||||
] $m_axi_misc0
|
||||
|
||||
set m_axi_misc1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_misc1 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ADDR_WIDTH {40} \
|
||||
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
|
||||
CONFIG.DATA_WIDTH {32} \
|
||||
CONFIG.FREQ_HZ {40000000} \
|
||||
CONFIG.HAS_BURST {0} \
|
||||
CONFIG.HAS_CACHE {0} \
|
||||
CONFIG.HAS_LOCK {0} \
|
||||
CONFIG.HAS_QOS {0} \
|
||||
CONFIG.HAS_REGION {0} \
|
||||
CONFIG.PROTOCOL {AXI4LITE} \
|
||||
] $m_axi_misc1
|
||||
|
||||
set m_axi_misc2 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_misc2 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ADDR_WIDTH {40} \
|
||||
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
|
||||
CONFIG.DATA_WIDTH {32} \
|
||||
CONFIG.FREQ_HZ {40000000} \
|
||||
CONFIG.HAS_BURST {0} \
|
||||
CONFIG.HAS_CACHE {0} \
|
||||
CONFIG.HAS_LOCK {0} \
|
||||
CONFIG.HAS_QOS {0} \
|
||||
CONFIG.HAS_REGION {0} \
|
||||
CONFIG.PROTOCOL {AXI4LITE} \
|
||||
] $m_axi_misc2
|
||||
|
||||
set m_axi_misc3 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_misc3 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ADDR_WIDTH {40} \
|
||||
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
|
||||
CONFIG.DATA_WIDTH {32} \
|
||||
CONFIG.FREQ_HZ {40000000} \
|
||||
CONFIG.HAS_BURST {0} \
|
||||
CONFIG.HAS_CACHE {0} \
|
||||
CONFIG.HAS_LOCK {0} \
|
||||
CONFIG.HAS_QOS {0} \
|
||||
CONFIG.HAS_REGION {0} \
|
||||
CONFIG.PROTOCOL {AXI4LITE} \
|
||||
] $m_axi_misc3
|
||||
|
||||
set s_axi_eth [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_eth ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ADDR_WIDTH {40} \
|
||||
CONFIG.ARUSER_WIDTH {0} \
|
||||
CONFIG.AWUSER_WIDTH {0} \
|
||||
CONFIG.BUSER_WIDTH {0} \
|
||||
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
|
||||
CONFIG.DATA_WIDTH {32} \
|
||||
CONFIG.FREQ_HZ {40000000} \
|
||||
CONFIG.HAS_BRESP {1} \
|
||||
CONFIG.HAS_BURST {0} \
|
||||
CONFIG.HAS_CACHE {0} \
|
||||
CONFIG.HAS_LOCK {0} \
|
||||
CONFIG.HAS_PROT {1} \
|
||||
CONFIG.HAS_QOS {0} \
|
||||
CONFIG.HAS_REGION {0} \
|
||||
CONFIG.HAS_RRESP {1} \
|
||||
CONFIG.HAS_WSTRB {1} \
|
||||
CONFIG.ID_WIDTH {0} \
|
||||
CONFIG.MAX_BURST_LENGTH {1} \
|
||||
CONFIG.NUM_READ_OUTSTANDING {8} \
|
||||
CONFIG.NUM_READ_THREADS {4} \
|
||||
CONFIG.NUM_WRITE_OUTSTANDING {8} \
|
||||
CONFIG.NUM_WRITE_THREADS {4} \
|
||||
CONFIG.PROTOCOL {AXI4LITE} \
|
||||
CONFIG.READ_WRITE_MODE {READ_WRITE} \
|
||||
CONFIG.RUSER_BITS_PER_BYTE {0} \
|
||||
CONFIG.RUSER_WIDTH {0} \
|
||||
CONFIG.SUPPORTS_NARROW_BURST {0} \
|
||||
CONFIG.WUSER_BITS_PER_BYTE {0} \
|
||||
CONFIG.WUSER_WIDTH {0} \
|
||||
] $s_axi_eth
|
||||
|
||||
|
||||
# Create ports
|
||||
set clk40 [ create_bd_port -dir I -type clk clk40 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ASSOCIATED_BUSIF {m_axi_misc0:m_axi_mac0:s_axi_eth:m_axi_misc3:m_axi_mac3:m_axi_dma1:m_axi_misc1:m_axi_mac2:m_axi_dma2:m_axi_mac1:m_axi_misc2:m_axi_dma0:m_axi_dma3} \
|
||||
CONFIG.ASSOCIATED_RESET {clk40_rstn} \
|
||||
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
|
||||
CONFIG.FREQ_HZ {40000000} \
|
||||
] $clk40
|
||||
set clk40_rstn [ create_bd_port -dir I -type rst clk40_rstn ]
|
||||
|
||||
# Create instance: axi_interconnect_0, and set properties
|
||||
set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.NUM_MI {12} \
|
||||
] $axi_interconnect_0
|
||||
|
||||
# Create interface connections
|
||||
connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_ports s_axi_eth] [get_bd_intf_pins axi_interconnect_0/S00_AXI]
|
||||
connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_ports m_axi_misc0] [get_bd_intf_pins axi_interconnect_0/M00_AXI]
|
||||
connect_bd_intf_net -intf_net axi_interconnect_0_M01_AXI [get_bd_intf_ports m_axi_mac0] [get_bd_intf_pins axi_interconnect_0/M01_AXI]
|
||||
connect_bd_intf_net -intf_net axi_interconnect_0_M02_AXI [get_bd_intf_ports m_axi_dma0] [get_bd_intf_pins axi_interconnect_0/M02_AXI]
|
||||
connect_bd_intf_net -intf_net axi_interconnect_0_M03_AXI [get_bd_intf_ports m_axi_misc1] [get_bd_intf_pins axi_interconnect_0/M03_AXI]
|
||||
connect_bd_intf_net -intf_net axi_interconnect_0_M04_AXI [get_bd_intf_ports m_axi_mac1] [get_bd_intf_pins axi_interconnect_0/M04_AXI]
|
||||
connect_bd_intf_net -intf_net axi_interconnect_0_M05_AXI [get_bd_intf_ports m_axi_dma1] [get_bd_intf_pins axi_interconnect_0/M05_AXI]
|
||||
connect_bd_intf_net -intf_net axi_interconnect_0_M06_AXI [get_bd_intf_ports m_axi_misc2] [get_bd_intf_pins axi_interconnect_0/M06_AXI]
|
||||
connect_bd_intf_net -intf_net axi_interconnect_0_M07_AXI [get_bd_intf_ports m_axi_mac2] [get_bd_intf_pins axi_interconnect_0/M07_AXI]
|
||||
connect_bd_intf_net -intf_net axi_interconnect_0_M08_AXI [get_bd_intf_ports m_axi_dma2] [get_bd_intf_pins axi_interconnect_0/M08_AXI]
|
||||
connect_bd_intf_net -intf_net axi_interconnect_0_M09_AXI [get_bd_intf_ports m_axi_misc3] [get_bd_intf_pins axi_interconnect_0/M09_AXI]
|
||||
connect_bd_intf_net -intf_net axi_interconnect_0_M10_AXI [get_bd_intf_ports m_axi_mac3] [get_bd_intf_pins axi_interconnect_0/M10_AXI]
|
||||
connect_bd_intf_net -intf_net axi_interconnect_0_M11_AXI [get_bd_intf_ports m_axi_dma3] [get_bd_intf_pins axi_interconnect_0/M11_AXI]
|
||||
|
||||
# Create port connections
|
||||
connect_bd_net -net clk40_1 [get_bd_ports clk40] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK] [get_bd_pins axi_interconnect_0/M02_ACLK] [get_bd_pins axi_interconnect_0/M03_ACLK] [get_bd_pins axi_interconnect_0/M04_ACLK] [get_bd_pins axi_interconnect_0/M05_ACLK] [get_bd_pins axi_interconnect_0/M06_ACLK] [get_bd_pins axi_interconnect_0/M07_ACLK] [get_bd_pins axi_interconnect_0/M08_ACLK] [get_bd_pins axi_interconnect_0/M09_ACLK] [get_bd_pins axi_interconnect_0/M10_ACLK] [get_bd_pins axi_interconnect_0/M11_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK]
|
||||
connect_bd_net -net clk40_rstn_1 [get_bd_ports clk40_rstn] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/M02_ARESETN] [get_bd_pins axi_interconnect_0/M03_ARESETN] [get_bd_pins axi_interconnect_0/M04_ARESETN] [get_bd_pins axi_interconnect_0/M05_ARESETN] [get_bd_pins axi_interconnect_0/M06_ARESETN] [get_bd_pins axi_interconnect_0/M07_ARESETN] [get_bd_pins axi_interconnect_0/M08_ARESETN] [get_bd_pins axi_interconnect_0/M09_ARESETN] [get_bd_pins axi_interconnect_0/M10_ARESETN] [get_bd_pins axi_interconnect_0/M11_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN]
|
||||
|
||||
# Create address segments
|
||||
create_bd_addr_seg -range 0x00008000 -offset 0x00000000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_dma0/Reg] SEG_m_axi_dma0_Reg
|
||||
create_bd_addr_seg -range 0x00008000 -offset 0x00010000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_dma1/Reg] SEG_m_axi_dma1_Reg
|
||||
create_bd_addr_seg -range 0x00008000 -offset 0x00020000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_dma2/Reg] SEG_m_axi_dma2_Reg
|
||||
create_bd_addr_seg -range 0x00008000 -offset 0x00030000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_dma3/Reg] SEG_m_axi_dma3_Reg
|
||||
create_bd_addr_seg -range 0x00002000 -offset 0x0000C000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_mac0/Reg] SEG_m_axi_mac0_Reg
|
||||
create_bd_addr_seg -range 0x00002000 -offset 0x0001C000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_mac1/Reg] SEG_m_axi_mac1_Reg
|
||||
create_bd_addr_seg -range 0x00002000 -offset 0x0002C000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_mac2/Reg] SEG_m_axi_mac2_Reg
|
||||
create_bd_addr_seg -range 0x00002000 -offset 0x0003C000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_mac3/Reg] SEG_m_axi_mac3_Reg
|
||||
create_bd_addr_seg -range 0x00004000 -offset 0x00008000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_misc0/Reg] SEG_m_axi_misc0_Reg
|
||||
create_bd_addr_seg -range 0x00004000 -offset 0x00018000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_misc1/Reg] SEG_m_axi_misc1_Reg
|
||||
create_bd_addr_seg -range 0x00004000 -offset 0x00028000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_misc2/Reg] SEG_m_axi_misc2_Reg
|
||||
create_bd_addr_seg -range 0x00004000 -offset 0x00038000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_misc3/Reg] SEG_m_axi_misc3_Reg
|
||||
|
||||
|
||||
# Restore current instance
|
||||
current_bd_instance $oldCurInst
|
||||
|
||||
validate_bd_design
|
||||
save_bd_design
|
||||
}
|
||||
# End of create_root_design()
|
||||
|
||||
|
||||
##################################################################
|
||||
# MAIN FLOW
|
||||
##################################################################
|
||||
|
||||
create_root_design ""
|
||||
|
||||
|
||||
Reference in New Issue
Block a user