fpga: x400: Add support for X410 motherboard FPGA
Co-authored-by: Andrew Moch <Andrew.Moch@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Michael Auchter <michael.auchter@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Hector Rubio <hrubio@ni.com> Original-commit: 6d3765605262016a80f71e36357f749ea35cbe5a
This commit is contained in:
Wade Fife
committed by
Aaron Rossetto
Aaron Rossetto
co-authored by
Andrew Moch
Daniel Jepson
Javier Valenzuela
Joerg Hofrichter
Kumaran Subramoniam
Max Köhler
Michael Auchter
Paul Butler
Hector Rubio
Andrew Moch
Daniel Jepson
Javier Valenzuela
Joerg Hofrichter
Kumaran Subramoniam
Max Köhler
Michael Auchter
Paul Butler
Hector Rubio
parent
bfef20ea45
commit
61782b02d7
@@ -0,0 +1,31 @@
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#
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# Copyright 2021 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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include $(TOOLS_DIR)/make/viv_ip_builder.mak
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IP_AXI_ETH_DMA_BD_HDL_SRCS = $(addprefix $(IP_DIR)/axi_eth_dma_bd/, \
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axi_eth_dma.sv \
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)
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IP_AXI_ETH_DMA_BD_ORIG_SRCS = $(addprefix $(IP_DIR)/axi_eth_dma_bd/, \
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axi_eth_dma_bd.tcl \
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)
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IP_AXI_ETH_DMA_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_eth_dma_bd/, \
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axi_eth_dma_bd.tcl \
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)
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IP_AXI_ETH_DMA_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_eth_dma_bd/, \
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axi_eth_dma_bd/axi_eth_dma_bd.bd \
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)
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BD_AXI_ETH_DMA_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_eth_dma_bd/, \
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axi_eth_dma_bd.bd.out \
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axi_eth_dma_bd/synth/axi_eth_dma_bd.v \
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)
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$(IP_AXI_ETH_DMA_BD_SRCS) $(BD_AXI_ETH_DMA_BD_OUTS) $(IP_AXI_ETH_DMA_BDTCL_SRCS): $(IP_AXI_ETH_DMA_BD_ORIG_SRCS)
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$(call BUILD_VIVADO_BDTCL,axi_eth_dma_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi)
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@@ -0,0 +1,73 @@
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//
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// Copyright 2021 Ettus Research, A National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: axi_eth_dma
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//
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// Description: Wrapper for the Xilinx AXI DMA
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//
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module axi_eth_dma (
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// All interfaces on s_axi_eth_dma.clk domain
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AxiStreamIf.slave e2c, // from enet mac
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AxiStreamIf.master c2e, // to enet mac
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AxiLiteIf.slave s_axi_eth_dma, // Register interface
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AxiIf.master axi_hp, // DMA interface to host memory
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output logic eth_rx_irq,
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output logic eth_tx_irq
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);
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`include "../../../../lib/axi4lite_sv/axi_lite.vh"
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`include "../../../../lib/axi4s_sv/axi4s.vh"
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`include "../../../../lib/axi4_sv/axi.vh"
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// _v versions have no procedural assignment so they can drive a port.
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AxiLiteIf_v #(32,10)
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s_axi_eth_dma_v(.clk(s_axi_eth_dma.clk), .rst(s_axi_eth_dma.rst));
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AxiIf_v #(128,49)
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axi_hp_v(.clk(s_axi_eth_dma.clk), .rst(s_axi_eth_dma.rst));
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AxiStreamIf #(.DATA_WIDTH(c2e.DATA_WIDTH), .USER_WIDTH(c2e.USER_WIDTH), .TUSER(0))
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c2e_v (c2e.clk, c2e.rst);
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AxiStreamIf #(.DATA_WIDTH(e2c.DATA_WIDTH), .USER_WIDTH(e2c.USER_WIDTH), .TUSER(0))
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e2c_v (e2c.clk, e2c.rst);
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always_comb begin
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// O = I; (O , I )
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`AXI4LITE_ASSIGN(s_axi_eth_dma_v, s_axi_eth_dma)
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// Overriding assignments to mask off upper address bits
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s_axi_eth_dma_v.araddr = 0;
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s_axi_eth_dma_v.araddr[9:0] = s_axi_eth_dma.araddr[9:0];
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s_axi_eth_dma_v.awaddr = 0;
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s_axi_eth_dma_v.awaddr[9:0] = s_axi_eth_dma.awaddr[9:0];
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end
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always_comb begin `AXI4S_ASSIGN(e2c_v, e2c) end
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always_comb begin `AXI4S_ASSIGN(c2e, c2e_v) end
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always_comb begin `AXI4_ASSIGN(axi_hp, axi_hp_v) end
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axi_eth_dma_bd axi_eth_dma_bd_i (
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.clk40 (s_axi_eth_dma.clk),
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.clk40_rstn (!s_axi_eth_dma.rst),
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.c2e_tdata (c2e_v.tdata),
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.c2e_tkeep (c2e_v.tkeep),
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.c2e_tlast (c2e_v.tlast),
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.c2e_tready (c2e_v.tready),
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.c2e_tvalid (c2e_v.tvalid),
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.e2c_tdata (e2c_v.tdata),
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.e2c_tkeep (e2c_v.tkeep),
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.e2c_tlast (e2c_v.tlast),
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.e2c_tready (e2c_v.tready),
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.e2c_tvalid (e2c_v.tvalid),
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`AXI4LITE_PORT_ASSIGN_NRS(axi_eth_dma, s_axi_eth_dma_v)
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`AXI4_PORT_ASSIGN_NR(axi_hp, axi_hp_v)
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.eth_tx_irq (eth_tx_irq),
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.eth_rx_irq (eth_rx_irq)
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);
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endmodule
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@@ -0,0 +1,325 @@
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################################################################
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# This is a generated script based on design: axi_eth_dma_bd
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#
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# Though there are limitations about the generated script,
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# the main purpose of this utility is to make learning
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# IP Integrator Tcl commands easier.
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################################################################
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namespace eval _tcl {
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proc get_script_folder {} {
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set script_path [file normalize [info script]]
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set script_folder [file dirname $script_path]
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return $script_folder
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}
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}
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variable script_folder
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set script_folder [_tcl::get_script_folder]
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################################################################
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# Check if script is running in correct Vivado version.
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################################################################
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set scripts_vivado_version 2019.1
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set current_vivado_version [version -short]
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if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
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puts ""
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catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
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return 1
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}
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################################################################
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# START
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################################################################
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# To test this script, run the following commands from Vivado Tcl console:
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# source axi_eth_dma_bd_script.tcl
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# If there is no project opened, this script will create a
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# project, but make sure you do not have an existing project
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# <./myproj/project_1.xpr> in the current working folder.
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set list_projs [get_projects -quiet]
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if { $list_projs eq "" } {
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create_project project_1 myproj -part xczu28dr-ffvg1517-1-e
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}
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# CHANGE DESIGN NAME HERE
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variable design_name
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set design_name axi_eth_dma_bd
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# If you do not already have an existing IP Integrator design open,
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# you can create a design using the following command:
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# create_bd_design $design_name
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# Creating design if needed
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set errMsg ""
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set nRet 0
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set cur_design [current_bd_design -quiet]
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set list_cells [get_bd_cells -quiet]
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if { ${design_name} eq "" } {
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# USE CASES:
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# 1) Design_name not set
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set errMsg "Please set the variable <design_name> to a non-empty value."
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set nRet 1
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} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
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# USE CASES:
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# 2): Current design opened AND is empty AND names same.
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# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
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# 4): Current design opened AND is empty AND names diff; design_name exists in project.
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if { $cur_design ne $design_name } {
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common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
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set design_name [get_property NAME $cur_design]
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}
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common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
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} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
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# USE CASES:
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# 5) Current design opened AND has components AND same names.
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set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
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set nRet 1
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} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
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# USE CASES:
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# 6) Current opened design, has components, but diff names, design_name exists in project.
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# 7) No opened design, design_name exists in project.
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set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
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set nRet 2
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} else {
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# USE CASES:
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# 8) No opened design, design_name not in project.
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# 9) Current opened design, has components, but diff names, design_name not in project.
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common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
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create_bd_design $design_name
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common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
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current_bd_design $design_name
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}
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common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
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if { $nRet != 0 } {
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catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
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return $nRet
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}
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set bCheckIPsPassed 1
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##################################################################
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# CHECK IPs
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##################################################################
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set bCheckIPs 1
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if { $bCheckIPs == 1 } {
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set list_check_ips "\
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xilinx.com:ip:axi_dma:7.1\
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xilinx.com:ip:smartconnect:1.0\
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"
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set list_ips_missing ""
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common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
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foreach ip_vlnv $list_check_ips {
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set ip_obj [get_ipdefs -all $ip_vlnv]
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if { $ip_obj eq "" } {
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lappend list_ips_missing $ip_vlnv
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}
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}
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if { $list_ips_missing ne "" } {
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catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
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set bCheckIPsPassed 0
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}
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}
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if { $bCheckIPsPassed != 1 } {
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common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
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return 3
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}
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##################################################################
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# DESIGN PROCs
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##################################################################
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# Procedure to create entire design; Provide argument to make
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# procedure reusable. If parentCell is "", will use root.
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proc create_root_design { parentCell } {
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variable script_folder
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variable design_name
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if { $parentCell eq "" } {
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set parentCell [get_bd_cells /]
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}
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# Get object for parentCell
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set parentObj [get_bd_cells $parentCell]
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if { $parentObj == "" } {
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catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
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return
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}
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# Make sure parentObj is hier blk
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set parentType [get_property TYPE $parentObj]
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if { $parentType ne "hier" } {
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catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
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return
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}
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# Save current instance; Restore later
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set oldCurInst [current_bd_instance .]
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# Set parent object as current
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current_bd_instance $parentObj
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# Create interface ports
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set axi_eth_dma [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 axi_eth_dma ]
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set_property -dict [ list \
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CONFIG.ADDR_WIDTH {40} \
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CONFIG.ARUSER_WIDTH {0} \
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CONFIG.AWUSER_WIDTH {0} \
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CONFIG.BUSER_WIDTH {0} \
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CONFIG.DATA_WIDTH {32} \
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CONFIG.FREQ_HZ {40000000} \
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CONFIG.HAS_BRESP {1} \
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CONFIG.HAS_BURST {0} \
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CONFIG.HAS_CACHE {0} \
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CONFIG.HAS_LOCK {0} \
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CONFIG.HAS_PROT {0} \
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CONFIG.HAS_QOS {0} \
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CONFIG.HAS_REGION {0} \
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CONFIG.HAS_RRESP {1} \
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CONFIG.HAS_WSTRB {0} \
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CONFIG.ID_WIDTH {0} \
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CONFIG.MAX_BURST_LENGTH {1} \
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CONFIG.NUM_READ_OUTSTANDING {8} \
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CONFIG.NUM_READ_THREADS {1} \
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CONFIG.NUM_WRITE_OUTSTANDING {8} \
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CONFIG.NUM_WRITE_THREADS {1} \
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CONFIG.PROTOCOL {AXI4LITE} \
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CONFIG.READ_WRITE_MODE {READ_WRITE} \
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CONFIG.RUSER_BITS_PER_BYTE {0} \
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CONFIG.RUSER_WIDTH {0} \
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CONFIG.SUPPORTS_NARROW_BURST {0} \
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CONFIG.WUSER_BITS_PER_BYTE {0} \
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CONFIG.WUSER_WIDTH {0} \
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] $axi_eth_dma
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set axi_hp [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 axi_hp ]
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set_property -dict [ list \
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CONFIG.ADDR_WIDTH {49} \
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CONFIG.DATA_WIDTH {128} \
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CONFIG.FREQ_HZ {40000000} \
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CONFIG.HAS_REGION {0} \
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CONFIG.NUM_READ_OUTSTANDING {16} \
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CONFIG.NUM_WRITE_OUTSTANDING {16} \
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CONFIG.PROTOCOL {AXI4} \
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] $axi_hp
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set c2e [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 c2e ]
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set_property -dict [ list \
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CONFIG.FREQ_HZ {40000000} \
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] $c2e
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set e2c [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 e2c ]
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set_property -dict [ list \
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CONFIG.FREQ_HZ {40000000} \
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CONFIG.HAS_TKEEP {1} \
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CONFIG.HAS_TLAST {1} \
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CONFIG.HAS_TREADY {1} \
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CONFIG.HAS_TSTRB {0} \
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CONFIG.LAYERED_METADATA {undef} \
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CONFIG.TDATA_NUM_BYTES {8} \
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CONFIG.TDEST_WIDTH {0} \
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CONFIG.TID_WIDTH {0} \
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CONFIG.TUSER_WIDTH {0} \
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] $e2c
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# Create ports
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set clk40 [ create_bd_port -dir I -type clk clk40 ]
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set_property -dict [ list \
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CONFIG.ASSOCIATED_BUSIF {e2c:axi_eth_dma:axi_hp:c2e} \
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CONFIG.ASSOCIATED_RESET {clk40_rstn} \
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CONFIG.FREQ_HZ {40000000} \
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] $clk40
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set clk40_rstn [ create_bd_port -dir I -type rst clk40_rstn ]
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set eth_rx_irq [ create_bd_port -dir O -type intr eth_rx_irq ]
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set eth_tx_irq [ create_bd_port -dir O -type intr eth_tx_irq ]
|
||||
|
||||
# Create instance: axi_eth_dma, and set properties
|
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set axi_eth_dma [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_eth_dma ]
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||||
set_property -dict [ list \
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||||
CONFIG.c_addr_width {36} \
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||||
CONFIG.c_enable_multi_channel {0} \
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||||
CONFIG.c_include_mm2s_dre {1} \
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CONFIG.c_include_s2mm {1} \
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CONFIG.c_include_s2mm_dre {1} \
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CONFIG.c_m_axi_mm2s_data_width {64} \
|
||||
CONFIG.c_m_axi_s2mm_data_width {64} \
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||||
CONFIG.c_m_axis_mm2s_tdata_width {64} \
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||||
CONFIG.c_micro_dma {0} \
|
||||
CONFIG.c_mm2s_burst_size {8} \
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||||
CONFIG.c_s2mm_burst_size {16} \
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||||
CONFIG.c_sg_include_stscntrl_strm {0} \
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||||
] $axi_eth_dma
|
||||
|
||||
# Create instance: smartconnect_eth_dma, and set properties
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||||
set smartconnect_eth_dma [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_eth_dma ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.NUM_SI {3} \
|
||||
] $smartconnect_eth_dma
|
||||
|
||||
# Create interface connections
|
||||
connect_bd_intf_net -intf_net Conn3 [get_bd_intf_ports c2e] [get_bd_intf_pins axi_eth_dma/M_AXIS_MM2S]
|
||||
connect_bd_intf_net -intf_net Conn4 [get_bd_intf_ports e2c] [get_bd_intf_pins axi_eth_dma/S_AXIS_S2MM]
|
||||
connect_bd_intf_net -intf_net axi_eth_dma_internal_M_AXI_MM2S [get_bd_intf_pins axi_eth_dma/M_AXI_MM2S] [get_bd_intf_pins smartconnect_eth_dma/S01_AXI]
|
||||
connect_bd_intf_net -intf_net axi_eth_dma_internal_M_AXI_S2MM [get_bd_intf_pins axi_eth_dma/M_AXI_S2MM] [get_bd_intf_pins smartconnect_eth_dma/S02_AXI]
|
||||
connect_bd_intf_net -intf_net axi_eth_dma_internal_M_AXI_SG [get_bd_intf_pins axi_eth_dma/M_AXI_SG] [get_bd_intf_pins smartconnect_eth_dma/S00_AXI]
|
||||
connect_bd_intf_net -intf_net axi_interconnect_common_m_axi_eth_dma_ctrl [get_bd_intf_ports axi_eth_dma] [get_bd_intf_pins axi_eth_dma/S_AXI_LITE]
|
||||
connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_ports axi_hp] [get_bd_intf_pins smartconnect_eth_dma/M00_AXI]
|
||||
|
||||
# Create port connections
|
||||
connect_bd_net -net axi_eth_dma_mm2s_introut [get_bd_ports eth_tx_irq] [get_bd_pins axi_eth_dma/mm2s_introut]
|
||||
connect_bd_net -net axi_eth_dma_s2mm_introut [get_bd_ports eth_rx_irq] [get_bd_pins axi_eth_dma/s2mm_introut]
|
||||
connect_bd_net -net clk40 [get_bd_ports clk40] [get_bd_pins axi_eth_dma/m_axi_mm2s_aclk] [get_bd_pins axi_eth_dma/m_axi_s2mm_aclk] [get_bd_pins axi_eth_dma/m_axi_sg_aclk] [get_bd_pins axi_eth_dma/s_axi_lite_aclk] [get_bd_pins smartconnect_eth_dma/aclk]
|
||||
connect_bd_net -net clk40_rstn [get_bd_ports clk40_rstn] [get_bd_pins axi_eth_dma/axi_resetn] [get_bd_pins smartconnect_eth_dma/aresetn]
|
||||
|
||||
# Create address segments
|
||||
create_bd_addr_seg -range 0x001000000000 -offset 0x00000000 [get_bd_addr_spaces axi_eth_dma/Data_SG] [get_bd_addr_segs axi_hp/Reg] SEG_m_axi_to_ps_Reg
|
||||
create_bd_addr_seg -range 0x001000000000 -offset 0x00000000 [get_bd_addr_spaces axi_eth_dma/Data_MM2S] [get_bd_addr_segs axi_hp/Reg] SEG_m_axi_to_ps_Reg
|
||||
create_bd_addr_seg -range 0x001000000000 -offset 0x00000000 [get_bd_addr_spaces axi_eth_dma/Data_S2MM] [get_bd_addr_segs axi_hp/Reg] SEG_m_axi_to_ps_Reg
|
||||
create_bd_addr_seg -range 0x010000000000 -offset 0x00000000 [get_bd_addr_spaces axi_eth_dma] [get_bd_addr_segs axi_eth_dma/S_AXI_LITE/Reg] SEG_axi_eth_dma_Reg
|
||||
|
||||
|
||||
# Restore current instance
|
||||
current_bd_instance $oldCurInst
|
||||
|
||||
validate_bd_design
|
||||
save_bd_design
|
||||
}
|
||||
# End of create_root_design()
|
||||
|
||||
|
||||
##################################################################
|
||||
# MAIN FLOW
|
||||
##################################################################
|
||||
|
||||
create_root_design ""
|
||||
|
||||
|
||||
@@ -0,0 +1,90 @@
|
||||
--
|
||||
-- Copyright 2021 Ettus Research, a National Instruments Brand
|
||||
--
|
||||
-- SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
--
|
||||
-- Module: axi_eth_dma_bd
|
||||
--
|
||||
-- Description:
|
||||
--
|
||||
-- This is an automatically generated stub file to match the entity
|
||||
-- declaration for 'axi_eth_dma_bd'. This file was created using
|
||||
-- niBdExportStub Do not modify this file directly!
|
||||
--
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
|
||||
entity axi_eth_dma_bd is
|
||||
port (
|
||||
clk40 : in STD_LOGIC;
|
||||
clk40_rstn : in STD_LOGIC;
|
||||
eth_rx_irq : out STD_LOGIC;
|
||||
eth_tx_irq : out STD_LOGIC;
|
||||
c2e_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
|
||||
c2e_tkeep : out STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
c2e_tlast : out STD_LOGIC;
|
||||
c2e_tready : in STD_LOGIC;
|
||||
c2e_tvalid : out STD_LOGIC;
|
||||
e2c_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
|
||||
e2c_tkeep : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
e2c_tlast : in STD_LOGIC;
|
||||
e2c_tready : out STD_LOGIC;
|
||||
e2c_tvalid : in STD_LOGIC;
|
||||
axi_eth_dma_araddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
|
||||
axi_eth_dma_arready : out STD_LOGIC;
|
||||
axi_eth_dma_arvalid : in STD_LOGIC;
|
||||
axi_eth_dma_awaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
|
||||
axi_eth_dma_awready : out STD_LOGIC;
|
||||
axi_eth_dma_awvalid : in STD_LOGIC;
|
||||
axi_eth_dma_bready : in STD_LOGIC;
|
||||
axi_eth_dma_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
axi_eth_dma_bvalid : out STD_LOGIC;
|
||||
axi_eth_dma_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
axi_eth_dma_rready : in STD_LOGIC;
|
||||
axi_eth_dma_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
axi_eth_dma_rvalid : out STD_LOGIC;
|
||||
axi_eth_dma_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
axi_eth_dma_wready : out STD_LOGIC;
|
||||
axi_eth_dma_wvalid : in STD_LOGIC;
|
||||
axi_hp_awaddr : out STD_LOGIC_VECTOR ( 48 downto 0 );
|
||||
axi_hp_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
axi_hp_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
axi_hp_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
axi_hp_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
axi_hp_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
axi_hp_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
axi_hp_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
axi_hp_awvalid : out STD_LOGIC;
|
||||
axi_hp_awready : in STD_LOGIC;
|
||||
axi_hp_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
|
||||
axi_hp_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
axi_hp_wlast : out STD_LOGIC;
|
||||
axi_hp_wvalid : out STD_LOGIC;
|
||||
axi_hp_wready : in STD_LOGIC;
|
||||
axi_hp_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
axi_hp_bvalid : in STD_LOGIC;
|
||||
axi_hp_bready : out STD_LOGIC;
|
||||
axi_hp_araddr : out STD_LOGIC_VECTOR ( 48 downto 0 );
|
||||
axi_hp_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
axi_hp_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
axi_hp_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
axi_hp_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
axi_hp_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
axi_hp_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
axi_hp_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
axi_hp_arvalid : out STD_LOGIC;
|
||||
axi_hp_arready : in STD_LOGIC;
|
||||
axi_hp_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
|
||||
axi_hp_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
axi_hp_rlast : in STD_LOGIC;
|
||||
axi_hp_rvalid : in STD_LOGIC;
|
||||
axi_hp_rready : out STD_LOGIC
|
||||
);
|
||||
end entity axi_eth_dma_bd;
|
||||
|
||||
architecture stub of axi_eth_dma_bd is
|
||||
begin
|
||||
end architecture stub;
|
||||
Reference in New Issue
Block a user