fpga: x400: Add support for X410 motherboard FPGA

Co-authored-by: Andrew Moch <Andrew.Moch@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Michael Auchter <michael.auchter@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Hector Rubio <hrubio@ni.com> Original-commit: 6d3765605262016a80f71e36357f749ea35cbe5a
2021-06-10 11:56:58 -05:00
parent bfef20ea45
commit 61782b02d7
205 changed files with 299634 additions and 0 deletions
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+------------------------------------------------------------------------------------------
+--
+-- File: adc_400m_bd.vhd
+-- Author: niBlockDesign::niBdExportStub
+-- Original Project: HwBuildTools
+-- Date: 21 October 2020
+--
+------------------------------------------------------------------------------------------
+-- (c) Copyright National Instruments Corporation
+-- All Rights Reserved
+-- National Instruments Internal Information
+------------------------------------------------------------------------------------------
+--
+-- Purpose: This is an automatically generated stub file to match the entity
+-- declaration for 'adc_400m_bd'. This file was created using niBdExportStub
+-- Do not modify this file directly!
+--
+------------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+library unisim;
+use unisim.vcomponents.all;
+
+entity adc_400m_bd is
+port (
+    adc_data_out_resetn_dclk : in STD_LOGIC;
+    data_clk : in STD_LOGIC;
+    enable_data_to_fir_rclk : in STD_LOGIC;
+    fir_resetn_rclk2x : in STD_LOGIC;
+    rfdc_adc_axi_resetn_rclk : in STD_LOGIC;
+    rfdc_clk : in STD_LOGIC;
+    rfdc_clk_2x : in STD_LOGIC;
+    swap_iq_2x : in STD_LOGIC;
+    adc_q_data_in_tvalid : in STD_LOGIC;
+    adc_q_data_in_tready : out STD_LOGIC;
+    adc_q_data_in_tdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
+    adc_i_data_in_tvalid : in STD_LOGIC;
+    adc_i_data_in_tready : out STD_LOGIC;
+    adc_i_data_in_tdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
+    adc_data_out_tvalid : out STD_LOGIC;
+    adc_data_out_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 )
+  );
+  end entity adc_400m_bd;
+
+architecture stub of adc_400m_bd is
+begin
+end architecture stub;